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參數(shù)資料
| 型號： | PCK12429BD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 25-400 MHz differential PECL clock generator |
| 中文描述： | 400 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 128K |
| 代理商： | PCK12429BD |
Philips Semiconductors
Product data
PCK12429
25–400 MHz differential PECL clock generator
2002 Jun 03
4
32-Pin LQFP
24
23
22
21
20
19
18
17
9
1
1
1
1
1
1
1
N/C
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
1
2
3
4
5
6
7
8
3
3
3
2
2
2
2
2
32-LEAD LQFP
SW01012
S_CLOCK
S_DATA
S_LOAD
N/C
N/C
XTAL1
V
F
F
G
V
c
V
c
T
G
X
O
M
P
M
M
M
N
PLL-V
CC
c
PLL-V
CC
PIN DESCRIPTION
SYMBOL
FUNCTION
XTAL1, XTAL2
These pins form an oscillator when connected to an external series-resonant crystal.
S_LOAD (Int. pulldown)
This pin loads the configuration latches with the contents of the shift registers. The latches will be
transparent when this signal is HIGH, thus the data must be stable on the HIGH-to-LOW transition
of S_LOAD for proper operation.
S_DATA (Int. pulldown)
This pin acts as the data input to the serial configuration shift registers.
S_CLOCK (Int. pulldown)
This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the
rising edge.
This pin loads the configuration latches with the contents of the parallel inputs. The latches will be
transparent when this signal is LOW, thus the parallel data must be stable on the LOW-to-HIGH
transition of P_LOAD for proper operation.
P_LOAD (Int. pullup)
M[8:0] (Int. pullup)
These pins are used to configure the PLL loop divider. They are sampled on the LOW-to-HIGH
transition of P_LOAD, M[8] is the MSB, M[0] is the LSB.
These pins are used to configure the output divider modulus. They are sampled on the
LOW-to-HIGH transition of P_LOAD.
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse
generation on the F
OUT
output.
These differential positive-referenced ECL signals (PECL) are the output of the synthesizer.
N[1:0] (Int. pullup)
OE (Int. pullup)
F
OUT
, F
OUT
TEST
The function of this output is determined by the serial configuration bits T[2:0].
V
CC1
and V
CCO
This is the positive supply for the internal logic and the output buffer of the chip, and is connected to
+3.3 V (V
CC
= PLL_V
CC
).
This is the positive supply for the PLL, and should be as noise-free as possible for low-jitter
operation. This supply is connected to +3.3 V (V
CC
= PLL_V
CC
).
These pins are the negative supply for the chip and are normally all connected to ground.
PLL_V
CC
GND
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK12429BD,118 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 25-400MHZ DIFF PECL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PCK12429BD,151 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 25-400MHZ DIFF PECL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PCK12429BD,157 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 25-400MHZ DIFF PECL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PCK12429BD-S | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 25-400MHZ DIFF PECL CLOCK GEN RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PCK12429BD-T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 25-400MHZ DIFF PECL CLOCK GEN RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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