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參數(shù)資料
| 型號： | PCK12429BD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 25-400 MHz differential PECL clock generator |
| 中文描述： | 400 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大小： | 128K |
| 代理商： | PCK12429BD |
Philips Semiconductors
Product data
PCK12429
25–400 MHz differential PECL clock generator
2
2002 Jun 03
853-2312 28362
INTRODUCTION
The PCK12429 is a general purpose synthesized clock source
targeting applications that require both serial and parallel interfaces.
The differential PECL output can be configured to be the VCO
frequency divided by 1, 2, 4, or 8. With the output configured to
divide the VCO frequency by 2, and with a 16.000 MHz external
quartz crystal used to provide the reference frequency, the output
frequency can be specified in 1 MHz steps. The PLL loop filter is
fully integrated so that no external components are required.
FEATURES
25 to 400 MHz differential PECL outputs
±
25 ps peak-to-peak output jitter
Fully integrated phase-locked loop
Minimal frequency over-shoot
Synthesized architecture
Serial 3-wire interface
Parallel interface for power-up
Quartz crystal interface
Package offer: SO28, PLCC28, and LQFP32
Operates from 3.3 V power supply
DESCRIPTION
The internal oscillator uses the external quartz crystal as the basis
of its frequency reference. The output of the reference oscillator is
divided by 16 before being sent to the phase detector.
The VCO output is scaled by a divider that is configured by either
the serial or parallel interfaces. The output of this loop divider is also
applied to the phase detector.
The phase detector and loop filter attempt to force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low) the PLL will not achieve loop lock.
The output of the VCO is also passed through an output divider
before being sent to the PECL output driver. This output divider (N
divider) is configured through either the serial or the parallel
interfaces, and can provide one of four division ratios (1, 2, 4, or 8).
This divider extends performance of the part while providing a 50%
duty cycle.
The output driver is driven differentially from the output divider, and
is capable of driving a pair of transmission lines terminated in 50
to V
CC
–2.0. The positive reference for the output driver and the
internal logic is separated from the power supply for the
phase-locked loop to minimize noise induced jitter.
The configuration logic has two sections: serial and parallel. The
parallel interface uses the values at the M[8:0] and N[1:0] inputs to
configure the internal counters. Normally, on system reset, the
P_LOAD input is held LOW until sometime after power becomes
valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs
are captured. The parallel interface has priority over the serial
interface. Internal pullup resistors are provided on the M[8:0] and
N[1:0] inputs to reduce component count in the application of the
chip.
The serial interface centers on a fourteen bit shift register. The shift
register shifts once per rising edge of the S_CLOCK input. The
serial input S_DATA must meet setup and hold timing as specified in
the AC Characteristics section of this document. The configuration
latches will capture the value of the shift register on the
HIGH-to-LOW edge of the S_LOAD input. See the programming
section for more information.
The TEST output reflects various internal node values, and is
controlled by the T[2:0] bits in the serial data stream. See the
programming section for more information.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
0 to +70
°
C
0 to +70
°
C
0 to +70
°
C
ORDER CODE
DRAWING NUMBER
28-Pin Plastic SO
PCK12429D
SOT136-1
28-Pin Plastic PLCC
PCK12429A
SOT261-2
32-pin Plastic LQFP
PCK12429BD
SOT358-1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCK12429D | 25-400 MHz differential PECL clock generator |
| PCK2000MDB | CK97 66/100MHz Mobile System Clock Generator |
| PCK2001MDB | 14.318-150 MHz I2C 1:10 Clock Buffer |
| PCK2002M | 0-300 MHz I2C 1:10 clock buffer |
| PCK2002MDB | 0-300 MHz I2C 1:10 clock buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK12429BD,118 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 25-400MHZ DIFF PECL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PCK12429BD,151 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 25-400MHZ DIFF PECL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PCK12429BD,157 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 25-400MHZ DIFF PECL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PCK12429BD-S | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 25-400MHZ DIFF PECL CLOCK GEN RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PCK12429BD-T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 25-400MHZ DIFF PECL CLOCK GEN RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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