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參數(shù)資料
| 型號： | PCI7610LQFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC Card, UltraMedia, and Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller |
| 中文描述： | PC卡，UltraMedia和集成1394 - 2000 OHCI的雙端口的PHY /鏈路層控制器 |
| 文件頁數(shù)： | 46/240頁 |
| 文件大?。?/td> | 1298K |
| 代理商： | PCI7610LQFP |
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signals. The core power supply is 1.8 V and is independent of the clamping voltages. For example, PCI signaling can
be either 3.3 V or 5 V, and the PCI7610 controller must reliably accommodate both voltage levels. This is
accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system
designer desires a 5-V PCI bus, then V
CCP
can be connected to a 5-V power supply.
3.5
Peripheral Component Interconnect (PCI) Interface
The PCI7610 controller is fully compliant with the
PCI Local Bus Specification
. The PCI7610 controller provides all
required signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment
by connecting the V
CCP
terminals to the desired voltage level. In addition to the mandatory PCI signals, the PCI7610
controller provides the optional interrupt signals INTA, INTB, and INTC for functions 0, 1, and 2, respectively.
3.5.1
1394 PCI Bus Master
As a bus master, the 1394 function of the PCI7610 controller supports the memory commands specified in Table 31
below. The PCI master supports the memory read, memory read line, and memory read multiple commands. The
read command usage for read transactions of greater than two data phases are determined by the selection in
bits 98 (MR_ENHANCE field) of the PCI miscellaneous configuration register (refer to Section 7.23 for details). For
read transactions of one or two data phases, a memory read command is used.
Table 31. PCI Bus Master Command Support
PCI
COMMAND
C/BE3C/BE0
OHCI MASTER FUNCTION
Memory read
0110
DMA read from memory
Memory write
0111
DMA write to memory
Memory read multiple
1100
DMA read from memory
Memory read line
1110
DMA read from memory
Memory write and invalidate
1111
DMA write to memory
3.5.2
PCI Bus Lock (LOCK)
The bus-locking protocol defined in the
PCI Local Bus Specification
is not highly recommended, but is provided on
the PCI7610 controller as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4
terminal by setting the appropriate values in bits 1916 of the multifunction routing status register. See Section 4.37,
Multifunction Routing Status Register
,
for details. Note that the use of LOCK is only supported by PCI-to-CardBus
bridges in the downstream direction (away from the processor).
PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted,
nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on
the PCI bus does not assure control of LOCK; control of LOCK is obtained under its own protocol. It is possible for
different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus signal
for this protocol is CBLOCK to avoid confusion with the bus clock.
An agent may need to do an exclusive operation because a critical access to memory might be broken into several
transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by
PCI to be 16 bytes, aligned. The LOCK protocol defined by the
PCI Local Bus Specification
allows a resource lock
without interfering with nonexclusive real-time data transfer, such as video.
The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario,
the arbiter does not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A
complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete
bus LOCK must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked
operation is in progress.
The PCI7610 controller supports all LOCK protocols associated with PCI-to-PCI bridges, as also defined for
PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve
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