參數(shù)資料
型號(hào)： PCI4515ZHK
廠商： Texas Instruments, Inc.
英文描述： SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED
中文描述： 單插槽CardBus控制器，它集成
文件頁(yè)數(shù)： 199/216頁(yè)
文件大?。?/td> 1138K
代理商： PCI4515ZHK
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95
Table 93. Link Enhancement Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
8
enab_dv_ts
RSC
Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV
CIP transmit streams (FMT = 00h). The default value for this bit is 0.
7
enab_unfair
RSC
Enable asynchronous priority requests. OHCI-Lynx
compatible. Setting bit 7 to 1 enables the link
to respond to requests with priority arbitration. It is recommended that this bit be set to 1. The default
value for this bit is 0.
6
RSVD
R
This bit is not assigned in the follow-on products, since this bit location loaded by the serial EEPROM
from the enhancements field corresponds to bit 23 (programPhyEnable) in the host controller control
register at OHCI offset 50h/54h (see Section 8.16).
53
RSVD
R
Reserved. Bits 53 return 0s when read.
2
RSVD
R
Reserved. Bit 2 returns 0 when read.
Enable acceleration enhancements. OHCI-Lynx
compatible. When bit 1 is set to 1, the PHY layer
is notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is,
ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1. The default
value for this bit is 0.
1
enab_accel
RSC
0
RSVD
R
Reserved. Bit 0 returns 0 when read.
This bit is cleared only by the assertion of GRST.
9.5
Timestamp Offset Register
The value of this register is added as an offset to the cycle timer value when using the MPEG, DV, and CIP
enhancements. A timestamp offset register is implemented per isochronous transmit context. The n value following
the offset indicates the context number (n = 0, 1, 2, 3,
…
, 7). These registers are programmed by software as
appropriate. See Table 94 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Timestamp offset
Type
RW
R
R
R
R
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Timestamp offset
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Timestamp offset
A90h + (4*n)
Read/Write, Read-only
0000 0000h
Table 94. Timestamp Offset Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
DisableInitialOffset
RW
Bit 31 disables the use of the initial timestamp offset when the MPEG2 enhancements are enabled.
A value of 0 indicates the use of the initial offset, a value of 1 indicates that the initial offset must not
be applied to the calculated timestamp. This bit has no meaning for the DV timestamp
enhancements. The default value for this bit is 0.
3025
RSVD
R
Reserved. Bits 3025 return 0s when read.
2412
CycleCount
RW
This field adds an offset to the cycle count field in the timestamp when the DV or MPEG2
enhancements are enabled. The cycle count field is incremented modulo 8000; therefore, values in
this field must be limited between 0 and 7999. The default value for this field is all 0s.
110
CycleOffset
RW
This field adds an offset to the cycle offset field in the timestamp when the DV or MPEG2
enhancements are enabled. The cycle offset field is incremented modulo 3072; therefore, values in
this field must be limited between 0 and 3071. The default value for this field is all 0s.
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