參數(shù)資料
型號(hào)： PCI2050GHK
英文描述： BUS CONTROLLER
中文描述： 總線控制器
文件頁(yè)數(shù)： 8/17頁(yè)
文件大?。?/td> 220K
代理商： PCI2050GHK
PCI2050A
PCI-to-PCI BRIDGE
SCPS067
–
MAY 2001
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
miscellaneous terminals
TERMINAL
NAME
I/O
DESCRIPTION
NO.
BPCCE
44
I
Bus/power clock control management terminal. When signal BPCCE is tied high, and when the
PCI2050 is placed in the D3 power state, it enables the PCI2050 to place the secondary bus in the
B2 power state. The PCI2050 disables the secondary clocks and drives them to 0. When tied low,
placing the PCI2050 in the D3 power state has no effect on the secondary bus clocks.
GPIO3/HSSWITCH
GPIO2
GPIO1
GPIO0
24
25
27
28
I
General-purpose I/O terminals
GPIO3 is HSSWITCH in cPCI mode.
HSSWITCH provides the status of the ejector handle switch to the cPCI logic.
HSENUM
127
O
Hot
–
swap ENUM
HSLED
128
O
Hot-swap LED output
MS0
155
I
Mode select 0
MS1
106
I
Mode select 1
P_M66ENA
102
I
Primary interface 66 MHz enable. This input-only signal pin is used to designate the primary interface
bus speed. This signal should be pulled low for 33 MHz operation on the primary bus. In this case
S_M66ENA signal will be driven low by the PCI2050A, forcing the secondary bus to run at 33 MHz.
For 66-MHz operation, this signal should be pulled high.
CONFIG66
125
I
Configure 66 MHz operation. This input-only pin is used to specify if PCI2050A is capable of running
at 66 MHz. If this terminal is tied high, then device can be run at 66 MHz. If this pin is tied low, then
PCI2050A can only function under the 33 MHz PCI specification.
S_M66ENA
153
I/O
Secondary 66-MHz enable terminal. This signal is used to designate the secondary bus speed. If the
P_M66ENA is driven low, then this signal is driven low by the PCI2050A forcing secondary bus to run
at 33 MHz. If the primary bus is running at 66 MHz (P_M66ENA is high), then S_M66ENA is an input
and should be externally pulled high for the secondary bus to operate at 66 MHz or pulled low for
secondary bus to operate at 33 MHz. Note that S_M66ENA is an open drained output.
JTAG interface terminals
TERMINAL
I/O
DESCRIPTION
NAME
NO.
TCK
133
I
JTAG boundary-scan clock. TCK is the clock controlling the JTAG logic.
TDI
129
I
JTAG serial data in. TDI is the serial input through which JTAG instructions and test data enter the JTAG
interface. The new data on TDI is sampled on the rising edge of TCK.
TDO
130
O
JTAG serial data out. TDO is the serial output through which test instructions and data from the test logic
leave the PCI2050.
TMS
132
I
JTAG test mode select. TMS causes state transitions in the test access port controller.
TRST
134
I
JTAG TAP reset. When TRST is asserted low, the TAP controller is asynchronously forced to enter a reset
state and initialize the test logic.
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