參數(shù)資料
型號(hào): PCI2050GHK
英文描述: BUS CONTROLLER
中文描述: 總線控制器
文件頁數(shù): 10/17頁
文件大?。?/td> 220K
代理商: PCI2050GHK
PCI2050A
PCI-to-PCI BRIDGE
SCPS067
MAY 2001
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
66-MHz operation
PCI2050A supports two 32-bit PCI buses operating at a maximum frequency of 66-MHz. The 66-MHz clocking
requires three terminals P_M66ENA, S_M66ENA and CONFIG66. To enable 66 MHz operation, the signal
CONFIG66 must be tied high on the board. This sets the 66 MHz capable bit in the primary and secondary status
register. The P_M66ENA and S_M66ENA must not be pulled high unless CONFIG66 is also high.
The signals P_ M66ENA and S_ M66ENA indicate whether the primary or secondary interfaces are working
at 66 MHz. This information is needed to control the frequency of the secondary bus. Note that PCI local bus
specification 2.2 restricts clock frequency changes above 33 MHz to during reset only.
The following frequency combinations are supported on the primary and secondary buses in PCI2050A:
66 MHz primary bus, 66 MHz secondary bus
66 MHz primary bus, 33 MHz secondary bus
33 MHz primary bus, 33 MHz secondary bus
The PCI2050A does not support 33-MHz primary/66-MHz secondary bus operation. If CONFIG66 is high and
P_M66ENA is low, the PCI2050A pulls down S_M66ENA to indicate that secondary bus is running at 33 MHz.
The 2050A generates the clock signals S_CLKOUT[9:0] for the secondary bus devices and its own interface.
It divides the P_CLK by two to generate the secondary clock outputs whenever the primary bus is running at
66 MHz and secondary bus is running at 33 MHz. The bridge detects this condition by polling P_M66ENA and
S_M66ENA.
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