參數(shù)資料
型號： PCI1510GVF
廠商： Texas Instruments, Inc.
英文描述： PC CARD CONTROLLERS
中文描述： PC卡控制器
文件頁數(shù)： 40/128頁
文件大小： 735K
代理商： PCI1510GVF
32
2.
Remove the clamp voltage.
3.
Remove the 3.3-V power from V
CC
.
NOTE:
The clamp voltage can be ramped up or ramped down along with the 3.3-V power. The
voltage difference between V
CC
and the clamp voltage must remain within 3.6 V.
3.2
I/O Characteristics
Figure 32 shows a 3-state bidirectional buffer. Section 7.2,
Recommended Operating Conditions
, provides the
electrical characteristics of the inputs and outputs.
NOTE:
The controller meets the ac specifications of the
PC Card Standard
and
PCI Local Bus
Specification.
Tied for Open Drain
OE
Pad
VCCP
Figure 32. 3-State Bidirectional Buffer
NOTE:
Unused terminals (input or I/O) must be held high or low to prevent them from floating.
3.3
Clamping Voltages
The clamping voltages are set to match whatever external environment the controller is interfaced with, 3.3 V or 5 V.
The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external signals.
The core power supply is always 3.3 V and is independent of the clamping voltages. For example, PCI signaling can
be either 3.3 V or 5 V, and the controller must reliably accommodate both voltage levels. This is accomplished by
using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system designer desires
a 5-V PCI bus, then V
CCP
can be connected to a 5-V power supply.
The controller requires three separate clamping voltages because it supports a wide range of features. The three
voltages are listed and defined in Section 7.2,
Recommended Operating Conditions
. GRST, SUSPEND, PME, and
CSTSCHG are not clamped to any of them.
3.4
Peripheral Component Interconnect (PCI) Interface
The controller is fully compliant with the
PCI Local Bus Specification
. The controller provides all required signals for
PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by connecting the V
CCP
terminal to the desired voltage level. In addition to the mandatory PCI signals, the controller provides the optional
interrupt signal INTA.
3.4.1
PCI GRST Signal
During the power-up sequence, GRST and PRST must be asserted. GRST can only be deasserted 100
μ
s after PCLK
is stable. PRST can be deasserted at the same time as GRST or any time thereafter.
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