參數(shù)資料
型號(hào)： PCF2113F2
廠商： NXP Semiconductors N.V.
英文描述： LCD controller/driver(LCD控制器/驅(qū)動(dòng)器)
中文描述： LCD控制器/驅(qū)動(dòng)器（液晶顯示控制器/驅(qū)動(dòng)器）
文件頁數(shù)： 7/60頁
文件大小： 392K
代理商： PCF2113F2
1997 Apr 04
7
Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
7
PIN FUNCTIONS
Note
1.
If the 4-bit interface is used without reading out from the PCF2113x (i.e. R/W is set permanently to logic 0), the
unused ports DB0 to DB3 can either be set to V
SS
or V
DD
instead of leaving them open.
NAME
FUNCTION
DESCRIPTION
RS
register select
RS selects the register to be accessed for read and write when the device is
controlled by the parallel interface. There is an internal pull-up on this pin.
RS = logic 0 selects the instruction register for write and the Busy Flag and Address
Counter for read.
RS = logic 1 selects the data register for both read and write.
R/W selects either the read (R/W = logic 1) or write (R/W = logic 0) operation when
the device is controlled by the parallel interface. There is an internal pull-up on this
pin.
The E pin is set HIGH to signal the start of a read or write operation when the device
is controlled by the parallel interface. Data is clocked in or out of the chip on the
negative edge of the clock. Note that this pin must be tied to logic 0 (V
SS
) when
I
2
C-bus control is used.
The parallel interface of the device. This bi-directional, 3-state data bus transfers
data between the system controller and the PCF2113x. There is an internal pull-up
on each of the data lines.
DB7 to DB0 must be connected to V
DD
or left open circuit when I
2
C-bus control is
used. Note that DB3 shares the same pin as SA0.
In 4-bit operations only DB7 to DB4 are used, and DB3 to DB0 must be left open
circuit. See note 1.
DB7 may be used as the Busy Flag, signalling that internal operations are not yet
completed.
These pins output the data for columns.
R/W
read/write
E
data bus clock
DB7 to DB0
data bus
C1 to C60
column driver
outputs
row driver
outputs
LCD power
supply
oscillator
R1 to R18
These pins output the row select waveforms to the display.
R17 and R18 drive the icons.
Positive power supply for the liquid crystal display. This may be generated on-chip or
supplied externally.
When the on-chip oscillator is used this pin must be connected to V
DD
.
An external clock signal, if used, is input at this pin.
Input for the I
2
C-bus clock signal.
SCL must be connected to V
SS
or V
DD
when the parallel interface is used.
I/O for the I
2
C-bus data line.
SDA must be connected to V
SS
or V
DD
when the parallel interface is used.
The hardware sub-address line is used to program the device sub-address for two
different PCF2113xs on the same I
2
C bus. Note that SA0 shares the same pin as
DB3.
T1 must be connected to V
SS
and is not user accessible.
power-down pad PD selects chip power-down mode. For normal operation PD = logic 0.
V
LCD
OSC
SCL
serial clock line
SDA
serial data line
SA0
address pin
T1
PD
test pad
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