1997 Apr 04
27
Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
9.8
Set DDRAM address
‘Set DDRAM address’ sets the DDRAM address (A
DD
in
Table 6) into the Address Counter (binary A[6] to A[0]).
Data can then be written to or read from the DDRAM.
9.9
Read busy flag and address
‘Read busy flag and address’ reads the Busy Flag (BF)
and Address Counter (AC). BF = logic 1 indicates that an
internal operation is in progress. The next instruction will
not be executed until BF = logic 0, so BF should be
checked before sending another instruction.
At the same time, the value of the Address Counter
expressed in binary A[6] to A[0] is read out. The Address
Counter is used by both CGRAM and DDRAM, and its
value is determined by the previous instruction.
9.10
Write data to CGRAM or DDRAM
‘Write data’ writes binary 8-bit data D[7] to D[0] to the
CGRAM or the DDRAM.
Whether the CGRAM or DDRAM is to be written into is
determined by the previous ‘Set CGRAM address’ or
‘Set DDRAM address’ instruction. After writing, the
address automatically increments or decrements by 1, in
accordance with the entry mode. Only bits D[4] to D[0] of
CGRAM data are valid, bits D[7] to D[5] are ‘don’t care’.
9.11
Read data from CGRAM or DDRAM
‘Read data’ reads binary 8-bit data D[7] to D[0] from the
CGRAM or DDRAM.
The most recent ‘Set address’ instruction determines
whether the CGRAM or DDRAM is to be read.
The ‘Read data’ instruction gates the content of the Data
Register (DR) to the bus while E is high. After E goes low
again, internal operation increments (or decrements) the
AC and stores RAM data corresponding to the new AC into
the DR.
Note: the only three instructions that update the Data
Register (DR) are:
‘Set CGRAM address’
‘Set DDRAM address’
‘Read data’ from CGRAM or DDRAM.
Other instructions (e.g. ‘Write data’, ‘Cursor/display shift’,
‘Clear display’, ‘Return home’) do not modify the data
register content.
10 EXTENDED FUNCTION SET INSTRUCTIONS AND
FEATURES
10.1
New instructions
H = logic 1 sets the chip into alternate instruction set
mode.
10.2
Icon control
The PCF2113x can drive up to 120 icons. See Fig.17 for
CGRAM to icon mapping.
10.3
IM
When IM = logic 0 the chip is in character mode. In
character mode characters and icons are driven
(MUX 1 : 18). The V
LCD
generator, if used, produces the
V
LCD
voltage programmed in register V
A
.
When IM = logic 1 the chip is in icon mode. In icon mode
only the icons are driven (MUX 1 : 2) and the V
LCD
voltage
generator, if used, produces the V
LCD
voltage
programmed in register V
B
.
Remark: If internally generated V
LCD
must not be lower
than V
DD
(V
DD
≤
4 V)
10.4
IB
Icon blink control is independent of the cursor/character
blink function.
When IB = logic 0 icon blink is disabled. Icon data is stored
in CGRAM character 0 to 2 (3
×
8
×
5 = 120 bits for
120 icons).
When IB = logic 1 icon blink is enabled. In this case each
icon is controlled by two bits. Blink consists of two half
phases (corresponding to the cursor on and off phases
called even and odd phases hereafter).
Icon states for the even phase are stored in CGRAM
characters 0 to 2 (3
×
8
×
5 = 120 bits for 120 icons).
These bits also define icon state when icon blink is not
used.
Icon states for the odd phase are stored in CGRAM
character 4 to 6 (another 120 bits for the 120 icons). When
icon blink is disabled CGRAM characters 4 to 6 may be
used as normal CGRAM characters.