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參數(shù)資料
| 型號： | PCE84C882 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontroller for monitor OSD and auto-sync applications(監(jiān)視器屏幕顯示和自動同步應(yīng)用的微控制器) |
| 中文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SDIP-42 |
| 文件頁數(shù)： | 8/60頁 |
| 文件大?。?/td> | 409K |
| 代理商： | PCE84C882 |
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1996 Jan 08
8
Philips Semiconductors
Preliminary specification
Microcontroller for monitor OSD
and auto-sync applications
PCE84C882
6
RESET
The RESET pin may be used as an active LOW input to
initialize the microcontroller to a defined state.
An active reset can be generated by driving theRESET pin
from an external logic device. Such an active reset pulse
should not fall off before V
DD
has reached its
f
xtal
-dependent minimum operating voltage.
A Power-on-reset can be generated using an external RC
circuit. To avoid overload of the internal diode, an external
diode should be added in parallel if C
RESET
≥
2.2
μ
F. The
RC circuit is shown in Fig.3.
6.1
Reset trip level
The RESET trip voltage level for the PCE84C882 is in the
range 0.7 to 1.9 V.
If any input (for example Hsync) goes HIGH before V
DD
is
applied, latch-up may occur and in this situation the
PCE84C882 cannot be reset. The cause and effect of
latch-up is shown in Fig.4.
6.2
Reset status
Derivative Registers reset status; see Table 38 for
details
Program Counter 00H
Memory Bank 0
Register Bank 0
Stack Pointer 00H
All interrupts disabled
Timer/event counter 1 stopped and cleared
Timer pre-scaler modulo-32 (PS = 0)
Timer flag cleared
Serial I/O interface disabled (ESO = 0) and in slave
receiver mode
Idle and Stop mode cleared.
Fig.3 External components for RESET pin.
handbook, halfpage
V
V
PCA84C8XX
internal reset
R
( 100 k
)
C
MLC259
DD
SS
RESET
RESET
RESET
Fig.4
The influence of an active HIGH signal being
applied before Power-on-reset.
handbook, halfpage
V
V
PCE84C882
internal reset
internal V
R
C
MGC710
DD
DD
VDD
SS
VSS
RESET
RESET
Hsync
HSYNCN
RESET
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