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參數(shù)資料
| 型號： | PCE84C882 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontroller for monitor OSD and auto-sync applications(監(jiān)視器屏幕顯示和自動同步應(yīng)用的微控制器) |
| 中文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SDIP-42 |
| 文件頁數(shù)： | 19/60頁 |
| 文件大小： | 409K |
| 代理商： | PCE84C882 |
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1996 Jan 08
19
Philips Semiconductors
Preliminary specification
Microcontroller for monitor OSD
and auto-sync applications
PCE84C882
9
ON SCREEN DISPLAY (OSD)
The OSD feature of the PCE84C882 enables the user to
display information on the monitor screen. Display
information can be created using 62 customer designed
characters, a space character and a carriage return code.
The OSD block diagram is shown in Fig.15.
9.1
Horizontal starting position control
The horizontal starting position counter is incremented
every OSD clock after Hsync becomes inactive and is
reset when Hsync becomes active. The horizontal starting
position of the display row is determined by the contents of
Register 36; 1 of 64 positions may be selected as
explained in Section 12.6.
The polarity of the active state of the HSYNCN input is
programmable and is determined by the Hp bit in
Register 34; see Section 12.4. The active HIGH and active
LOW states as selected by the Hp bit are shown in Fig.16.
9.2
Vertical starting position control
The vertical starting position counter is incremented every
Hsync cycle and is reset when Vsync becomes active. The
vertical starting position of the display row is determined by
the contents of Register 35; 1 of 64 positions may be
selected as explained in Section 12.5.
To achieve the same starting position with different display
resolutions, only the contents of Register 35 need to be
changed, the contents of Register 36 remain the same.
The lowest vertical starting position that can be selected,
is located on the 256th scan-line. However, lower positions
may be achieved using the Carriage Return Code.
When the selected horizontal and vertical starting
positions are reached on screen; the OSD is enabled. The
character selected in display RAM is then displayed.
The polarity of the active state of the VSYNCN input is
programmable and is determined by the Vp bit in Register
34; see Section 12.4. The active HIGH and active LOW
states as selected by the Vp bit are shown in Fig.16.
9.3
Vertical jumping cancelling
If the H-shift of the monitor is altered then vertical jumping
of the OSD may occur if the rising or falling edges of the
Hsync and Vsync signals are too close. The PCE84C882
has on-chip vertical cancelling circuitry that prevents this
from happening.
9.4
On-chip clock generator
The on-chip oscillator generates an OSD clock that is
auto-sync with Hsync. The frequency of the OSD clock is
programmable and is determined by the contents of the
7-bit counter (Register 25) and also the prescaler value
selected by mask option (a prescaler value of 2 or 4 can be
selected). For 31 to 64 kHz auto-sync monitors, a
prescaler value of 4 is selected; for 31 to 90 kHz auto-sync
monitors a prescaler value of 2 or 4 can be selected.
The OSD clock frequency is calculated as follows:
Where (Register 25) denotes the decimal value held in
Register 25.
The block diagram of the OSD clock is shown in Fig.17.
The internal reference frequency is connected to Hsync,
and if the frequency of Hsync changes the output
frequency (f
OSD
) will be changed linearly. The internal
Hsync signal is designed active HIGH, consequently f
PLL
is
synchronized with the falling edge of this signal (end of
back-tracing period).
The OSD clock is enabled/disabled by the state of the EN
bit in Register 34; see Section 12.4. When the OSD clock
is disabled the oscillator remains active, therefore the
transient time from the OSD clock start-up to locking into
the external Hsync signal is reduced. To ensure that the
OSD clock is stable and in-phase with Hsync before the
display is enabled, the End bit of the Space Code can be
used to enable the OSD feature; the procedure is as
follows.
1.
Write a Space Code to address 00H of display RAM,
the End bit value is logic 1.
Set the EN bit in Register 34 to logic 0.
Write a Space Code to address 00H of display RAM,
the End bit value is logic 0.
2.
3.
Two dedicated power pins: V
DDP
and V
SSP
, isolate the
oscillator supplies from other circuits thus reducing any
radiated noise that might effect the Voltage Controlled
Oscillator. Radiated noise is further reduced because as
the oscillator is always active after power-on when the
OSD clock is enabled no large currents will flow (as in the
case of RC or LC oscillators).
f
OSD
f
Hsync
2 or 4
(
)
Register 25
(
)
×
×
=
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