參數(shù)資料
型號(hào)： PCA9564
廠商： NXP Semiconductors N.V.
英文描述： Parallel bus to I2C-bus controller
中文描述： 并行總線I2C總線控制器
文件頁數(shù)： 5/31頁
文件大?。?/td> 222K
代理商： PCA9564
Philips Semiconductors
Product data
PCA9564
Parallel bus to I
2
C-bus controller
2003 Apr 02
5
FUNCTIONAL DESCRIPTION
General
The PCA9564 acts as an interface device between standard
high-speed parallel buses and the serial I
2
C-bus. On the I
2
C-bus, it
can act either as master or slave. Bidirectional data transfer between
the I
2
C-bus and the parallel-bus microcontroller is carried out on a
byte-wise basis, using either an interrupt or polled handshake.
Internal Oscillator
The PCA9564 contains an internal 9 MHz oscillator which is used
for all I
2
C timing. The oscillator requires up to 500
μ
s to start-up
after ENSIO bit is set to
“
1
”
.
Registers
The PCA9564 contains four registers which are used to configure
the operation of the device as well as to send and receive serial data.
The registers are selected by setting pins A0 and A1 to the
appropriate logic levels before a read or write operation is executed.
CAUTION:
and the SIO is in master or addressed slave mode.
Do not write to I
2
C registers while the I
2
C-bus is busy
REGISTER
NAME
I2CSTA
I2CTO
I2CDAT
I2CADR
I2CCON
REGISTER
FUNCTION
Status
Time-out
Data
Own address
Control
A1
A0
READ/
WRITE
R
W
R/W
R/W
R/W
DEFAULT
0
0
0
1
1
0
0
1
0
1
F8h
FFh
00h
00h
00h
The Time-out Register, I2CTO:
The time-out register is used to
determine the maximum time that SCL is allowed to be LOW before
the I
2
C state machine is reset.
When the I
2
C interface is operating, I2CTO is loaded in the time-out
counter at every SCL transition.
I2CTO
TE
Time-out value
7
6
5
4
3
2
1
0
TO6
TO5
TO4
TO3
TO2
TO1
TO0
The most significant bit of I2CTO (TE) is used as a time-out
enable/disable. A
“
1
”
will enable the time-out function. The time-out
period = (I2CTO[6:0] + 1)
×
113.7
μ
s. The time-out value may vary
some and is an approximate value.
The time-out register can be used in the following cases:
1.When the SIO, in the master mode, wants to send a START
condition and the SCL line is held LOW by some other device.
The SIO waits a time period equivalent to the time-out value for
the SCL to be released. In case it is not released, the SIO
concludes that there is a bus error, loads 90H in the I2CSTA
register, generates an interrupt signal and releases the SCL and
SDA lines. After the microcontroller reads the status register, it
needs to send an external reset in order to reset the SIO.
2.In the master mode, the time-out feature starts every time the SCL
goes LOW. If SCL stays LOW for a time period equal to or greater
than the time-out value, the SIO concludes there is a bus error
and behaves in the manner described above.
3.In case of a forced access to the I
2
C-bus. (See more details on
page 15.)
The Address Register, I2CADR:
I2CADR is not affected by the
SIO hardware. The contents of this register are irrelevant when SIO
is in a master mode. In the slave modes, the seven most significant
bits must be loaded with the microcontroller
’
s own slave address.
I2CADR
0
7
6
5
4
3
2
1
0
own slave address
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
The most significant bit corresponds to the first bit received from the
I
2
C-bus after a start condition. A logic 1 in I2CADR corresponds to a
HIGH level on the I
2
C-bus, and a logic 0 corresponds to a LOW
level on the bus. The least significant bit is not used but should be
programmed with a
‘
0
’
.
The Data Register, I2CDAT:
I2CDAT contains a byte of serial data
to be transmitted or a byte which has just been received. In master
mode, this includes the slave address that the master wants to send
out on the I
2
C-bus, with the most significant bit of the slave address
in the SD7 bit position and the Read/Write bit in the SD0 bit position.
The CPU can read from and write to this 8-bit register while it is not
in the process of shifting a byte. This occurs when SIO is in a
defined state and the serial interrupt flag is set. Data in I2CDAT
remains stable as long as SI is set. Whenever the SIO generates an
interrupt, the I2CDAT registers contain the data byte that was just
transferred on the I
2
C-bus.
NOTE:
The I2CDAT register will capture the serial address as data
when addressed via the serial bus. Also, the data register will
continue to capture data from the serial bus during 38H so the
I2CDAT register will need to be reloaded when the bus becomes
free.
I2CDAT
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
7
6
5
4
3
2
1
0
SD7 - SD0:
Eight bits to be transmitted or just received. A logic 1 in I2CDAT
corresponds to a HIGH level on the I
2
C-bus, and a logic 0
corresponds to a LOW level on the bus.
The Control Register, I2CCON:
The microcontroller can read from
and write to this 8-bit register. Two bits are affected by the SIO
hardware: the SI bit is set when a serial interrupt is requested, and
the STO bit is cleared when a STOP condition is present on the
I
2
C-bus.
I2CCON
ENSIO
,
THE
SIO E
NABLE
B
IT
ENSIO =
“
0
”
: When ENSIO is
“
0
”
, the SDA and SCL outputs are in a
high impedance state. SDA and SCL input signals are ignored, SIO
is in the
“
not addressed
”
slave state.
ENSIO
STA
STO
SI
CR1
CR0
7
6
5
4
3
2
1
0
CR2
AA
ENSIO =
“
1
”
: When ENSIO is
“
1
”
, SIO is enabled.
After the ENSIO bit is set, it takes 500
μ
s for the internal oscillator to
start up, therefore, the PCA9564 will enter either the master or the
slave mode after this time. ENSIO should not be used to temporarily
release the PCA9564 from the I
2
C-bus since, when ENSIO is reset,
the I
2
C-bus status is lost. The AA flag should be used instead (see
description of the AA flag in the following text).
In the following text, it is assumed that ENSIO =
“
1
”
.
STA
,
THE
START F
LAG
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PCA9564BS-T 功能描述:I2C 接口集成電路 400KHZ I2C BUS CTRLR RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16
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