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參數(shù)資料
| 型號： | PCA9564 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Parallel bus to I2C-bus controller |
| 中文描述： | 并行總線I2C總線控制器 |
| 文件頁數(shù)： | 3/31頁 |
| 文件大?。?/td> | 222K |
| 代理商： | PCA9564 |
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Philips Semiconductors
Product data
PCA9564
Parallel bus to I
2
C-bus controller
2003 Apr 02
3
PIN CONFIGURATION — SO, TSSOP
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20
D0
D1
D2
D3
D4
D5
D6
D7
DNU
V
SS
V
DD
SDA
SCL
RESET
INT
A1
A0
RD
CE
WR
10
su01485
PIN CONFIGURATION — HVQFN
15
14
13
12
11
6
7
8
9
1
1
2
3
4
5
2
1
1
1
1
su01665
TOP VIEW
D2
D3
D4
D5
D6
D7
DNU GND
(V
SS
)
WR
RD CE
INT
RESET
A0
A1
SCL
SDA
V
DD
D0
D1
PIN CONFIGURATION
PIN NUMBER
SO, TSSOP
HVQFN
SYMBOL
PIN
TYPE
I/O
NAME AND FUNCTION
1, 2, 3, 4, 5,
6, 7, 8
1, 2, 3, 4,
5, 18, 19,
20
D0-D7
Data Bus:
Bi-directional 3-State data bus used to transfer commands, data and status
between the controller and the CPU. D0 is the least significant bit.
9
6
DNU
Do not use: must be left floating (pulled low internally)
10
7
V
SS
WR
Pwr
Ground
11
8
I
Write Strobe:
When LOW and CE is also LOW, the contents of the data bus is loaded into
the addressed register. The transfer occurs on the rising edge of the signal.
12
9
RD
I
Read Strobe:
When LOW and CE is also LOW, causes the contents of the addressed
register to be presented on the data bus. The read cycle begins on the falling edge of RD.
13
10
CE
I
Chip Enable:
Active-LOW input signal. When LOW, data transfers between the CPU and
the controller are enabled on D0-D7 as controlled by the WR, RD and A0-A1 inputs.
When HIGH, places the D0-D7 lines in the 3-State condition.
14, 15
11, 12
A0, A1
I
Address Inputs:
Selects the controller internal registers and ports for read/write
operations.
16
13
INT
O
Interrupt Request:
Active-LOW, open-drain, output. This pin requires a pull-up device.
Reset:
A LOW level clears internal registers resets the I
2
C state machine.
I
2
C-bus serial clock input/output (open-drain).
I
2
C-bus serial data input/output (open-drain).
17
14
RESET
I
18
15
SCL
I/O
19
16
SDA
I/O
20
17
V
DD
Pwr
Power Supply:
2.3 to 3.6 V
相關PDF資料 |
PDF描述 |
|---|---|
| PCA9665 | Fm+ parallel bus to I2C-bus controller |
| PCA9665N | Fm+ parallel bus to I2C-bus controller |
| PCA9671 | Remote 16-bit I/O expander for Fm+ I2C-bus with reset |
| PCA9671DB | Remote 16-bit I/O expander for Fm+ I2C-bus with reset |
| PCA9671DK | Remote 16-bit I/O expander for Fm+ I2C-bus with reset |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PCA9564BS,118 | 功能描述:I2C 接口集成電路 400KHZ I2C BUS CTRLR RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
| PCA9564BS-T | 功能描述:I2C 接口集成電路 400KHZ I2C BUS CTRLR RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
| PCA9564D | 功能描述:I2C 接口集成電路 400KHZ I2C BUS CTRLR RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
| PCA9564D,112 | 功能描述:I2C 接口集成電路 400KHZ I2C BUS CTRLR RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
| PCA9564D,118 | 功能描述:I2C 接口集成電路 400 KHZ I2C BUS CONTROLLER RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
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