參數(shù)資料
型號: PCA9519
廠商: NXP Semiconductors N.V.
英文描述: 4-channel level translating I2C-bus/SMBus repeater
中文描述: 4通道級翻譯I2C-bus/SMBus中繼器
文件頁數(shù): 6/17頁
文件大?。?/td> 99K
代理商: PCA9519
PCA9519_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Objective data sheet
Rev. 01 — 22 June 2006
6 of 17
Philips Semiconductors
PCA9519
4-channel level translating I
2
C-bus/SMBus repeater
When port B of the PCA9519 is pulled LOW by a driver on the I
2
C-bus, a CMOS
hysteresis detects the falling edge when it goes below 0.3V
CC(B)
and causes the internal
driver on port A to turn on, causing port A to pull down to about 0.2 V. When port A of the
PCA9519 falls, first a comparator detects the falling edge and causes the internal driver
on port B to turn on and pull the port B pin down to ground. In order to illustrate what
would be seen in a typical application, refer to
Figure 5
and
Figure 6
. If the bus master in
Figure 4
were to write to the slave through the PCA9519, waveforms shown in
Figure 5
would be observed on the B bus. This looks like a normal I
2
C-bus transmission.
On the port A bus of the PCA9519, the clock and data lines would have a positive offset
from ground equal to the V
OL
of the PCA9519. After the 8
th
clock pulse, the data line will
be pulled to the V
OL
of the master device, which is very close to ground in this example. At
the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9519 for a short delay while the port B bus rises above 0.5V
CC(B)
, then it continues
HIGH. It is important to note that any arbitration or clock stretching events require that the
LOW level on the port A bus at the input of the PCA9519 (V
IL
) is below V
ILc
to be
recognized by the PCA9519 and then transmitted to the port B bus.
Fig 5.
Bus B SMBus/I
2
C-bus waveform
Fig 6.
Bus A lower voltage waveform
002aab644
9th clock pulse
acknowledge
SCL
SDA
002aab645
9th clock pulse
acknowledge
SCL
SDA
V
OL
of master
V
OL
of PCA9519
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