參數(shù)資料
型號(hào): PCA9519
廠商: NXP Semiconductors N.V.
英文描述: 4-channel level translating I2C-bus/SMBus repeater
中文描述: 4通道級(jí)翻譯I2C-bus/SMBus中繼器
文件頁數(shù): 5/17頁
文件大小: 99K
代理商: PCA9519
PCA9519_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Objective data sheet
Rev. 01 — 22 June 2006
5 of 17
Philips Semiconductors
PCA9519
4-channel level translating I
2
C-bus/SMBus repeater
go below its V
ILc
it will pull the port B LOW initially when the port A input transitions LOW
but port B will return HIGH, so it will not reproduce the port A input on port B. Such
applications should be avoided.
Port B is interoperable with all I
2
C-bus slaves, masters, and repeaters.
6.1 Enable
The EN pin is active HIGH and allows the user to select when the repeater is active. This
can be used to isolate a badly behaved slave on power-up until after the system power-up
reset. It should never change state during an I
2
C-bus operation because disabling during
a bus operation will hang the bus and enabling part way through a bus cycle could
confuse the I
2
C-bus parts being enabled.
The enable pin should only change state when the bus and the repeater port are in an idle
state to prevent system failures.
6.2 I
2
C-bus systems
As with the standard I
2
C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I
2
C-bus).
The size of these pull-up resistors depends on the system. Each of the port A I/Os has an
internal pull-up current source and does not require the external pull-up resistor. The
port B is designed to work with Standard mode and Fast mode I
2
C-bus devices in addition
to SMBus devices. Standard mode I
2
C-bus devices only specify 3 mA output drive; this
limits the termination current to 3 mA in a generic I
2
C-bus system where Standard mode
devices and multiple masters are possible. Under certain conditions higher termination
currents can be used.
7.
Application design-in information
A typical application is shown in
Figure 4
. In this example, the CPU is running on a 1.1 V
I
2
C-bus while the master is connected to a 3.3 V bus. Both buses run at 400 kHz. Master
devices can be placed on either bus.
Fig 4.
Typical application
002aab642
V
CC(B)
V
CC(A)
PCA9519
A1
B1
A2
B2
EN
10 k
10 k
SDA
SCL
CPU
MASTER
400 kHz
SDA
SCL
bus A
bus B
3.3 V
A8
B8
1.1 V
10 k
1.1 V
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