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參數(shù)資料
| 型號： | PC56F8006VWL |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 44/106頁 |
| 文件大小： | 0K |
| 描述： | DSP 16BIT 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 系列： | 56F8xxx |
| 核心處理器： | 56800 |
| 芯體尺寸： | 16-位 |
| 速度： | 32MHz |
| 連通性： | I²C，LIN，SCI，SPI |
| 外圍設(shè)備： | LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 23 |
| 程序存儲器容量： | 16KB（8K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 15x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 管件 |
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MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Specifications
Freescale Semiconductor
42
8.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified Table 12 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, take normal
precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability
of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the
programmable pullup resistor associated with the pin is enabled.
8.2.1
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, use
normal handling precautions to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices
can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM), and the
charge device model (CDM).
Table 12. Absolute Maximum Ratings
(VSS = 0 V, VSSA = 0 V)
Characteristic
Symbol
Notes
Min
Max
Unit
Supply Voltage Range
VDD
–0.3
3.8
V
Analog Supply Voltage Range
VDDA
–0.3
3.6
V
Voltage difference VDD to VDDA
V
DD
–0.3
0.3
V
Voltage difference VSS to VSSA
V
SS
–0.3
0.3
V
Digital Input Voltage Range
VIN
Pin Groups 1, 2
–0.3
VDD+0.3
V
Oscillator Voltage Range
VOSC
Pin Group 4
TBD
V
Analog Input Voltage Range
VINA
Pin Group 3
–0.3
3.6
V
Input clamp current, per pin (VIN < 0)
1 2 3
1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values.
2 All functional non-supply pins are internally clamped to V
SS and VDD.
3 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD loads shunt current greater than maximum injection
current. This is the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present or if the
clock rate is low (which would reduce overall power consumption).
VIC
—
–25.0
mA
Output clamp current, per pin (VO < 0)
1 2 3
VOC
—
–20.0
mA
Output Voltage Range
(Normal Push-Pull mode)
VOUT
Pin Group 1
–0.3
VDD
V
Ambient Temperature
Industrial
TA
–40
105
°C
Storage Temperature Range
(Extended Industrial)
TSTG
–55
150
°C
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