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| 型號： | PC56F8006VWL |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 35/106頁 |
| 文件大小： | 0K |
| 描述： | DSP 16BIT 28-SOIC |
| 標準包裝： | 26 |
| 系列： | 56F8xxx |
| 核心處理器： | 56800 |
| 芯體尺寸： | 16-位 |
| 速度： | 32MHz |
| 連通性： | I²C，LIN，SCI，SPI |
| 外圍設(shè)備： | LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 23 |
| 程序存儲器容量： | 16KB（8K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 15x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 管件 |
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MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
General System Control Information
Freescale Semiconductor
34
6
General System Control Information
6.1
Overview
This section discusses power pins, reset sources, interrupt sources, clock sources, the system integration module (SIM), ADC
synchronization, and JTAG/EOnCE interfaces.
6.2
Power Pins
VDD, VSS and VDDA, VSSA are the primary power supply pins for the devices. This voltage source supplies power to all on-chip
peripherals, I/O buffer circuitry and to internal voltage regulators. Device has multiple internal voltages provide regulated
lower-voltage source for the peripherals, core, memory, and on-chip relaxation oscillators.
Typically, there are at least two separate capacitors across the power pins to bypass the glitches and provide bulk charge storage.
In this case, there should be a bulk electrolytic or tantalum capacitor, such as a 10
F tantalum capacitor, to provide bulk charge
storage for the overall system and a 0.1
F ceramic bypass capacitor located as near to the device power pins as practical to
suppress high-frequency noise. Each pin must have a bypass capacitor for best noise suppression.
VDDA and VSSAare the analog power supply pins for the device. This voltage source supplies power to the ADC, PGA, and
CMP modules. A 0.1
F ceramic bypass capacitor should be located as near to the device VDDA and VSSA pins as practical to
suppress high-frequency noise. VDDA and VSSA are also the voltage reference high and voltage reference low inputs,
respectively, for the ADC module.
6.3
Reset
Resetting the device provides a way to start processing from a known set of initial conditions. During reset, most control and
status registers are forced to initial values and the program counter is loaded from the reset vector. On-chip peripheral modules
are disabled and I/O pins are initially configured as the reset status shown in Table 5. The 56F8006/56F8002 has the following
sources for reset:
Power-on reset (POR)
Partial power down reset (PPD)
Low-voltage detect (LVD)
External pin reset (EXTR)
Computer operating properly loss of reference reset (COP_LOR)
Computer operating properly time-out reset (COP_CPU)
Software Reset (SWR)
Each of these sources has an associated bit in the reset status register (RSTAT) in the system integration module (SIM).
The external pin reset function is shared with an GPIO port A7 on the RESET/GPIOA7 pin. The reset function is enabled
following any reset of the device. Bit 7 of GPIOA_PER register must be cleared to use this pin as an GPIO port pin. When
enabled as the RESET pin, an internal pullup device is automatically enabled.
6.4
On-chip Clock Synthesis
The on-chip clock synthesis (OCCS) module allows designers using an internal relaxation oscillator, an external crystal, or an
external clock to run 56F8000 family devices at user-selectable frequencies up to 32 MHz.
The features of OCCS module include:
Ability to power down the internal relaxation oscillator or crystal oscillator
Ability to put the internal relaxation oscillator into standby mode
Ability to power down the PLL
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