參數(shù)資料
型號(hào): PC48F4400P0VB00
廠商: INTEL CORP
元件分類(lèi): PROM
英文描述: Intel StrataFlash Embedded Memory
中文描述: 32M X 16 FLASH 1.8V PROM, 88 ns, PBGA64
封裝: LEAD FREE, BGA-64
文件頁(yè)數(shù): 37/102頁(yè)
文件大?。?/td> 1609K
代理商: PC48F4400P0VB00
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
37
R101
t
AVVH
Address setup to ADV# high
10
-
ns
1
R102
t
ELVH
CE# low to ADV# high
10
-
ns
R103
t
VLQV
ADV# low to output valid
Vcc = 1.8 V
– 2.0 V
-
85
ns
Vcc = 1.7 V
– 2.0 V
-
88
R104
t
VLVH
ADV# pulse width low
10
-
ns
R105
t
VHVL
ADV# pulse width high
10
-
ns
R106
t
VHAX
Address hold from ADV# high
9
-
ns
1,4
R108
t
APA
Page address access
-
25
ns
1
R111
t
phvh
RST# high to ADV# high
30
-
ns
Clock Specifications
R200
f
CLK
CLK frequency
-
40
MHz
1,3,6
R201
t
CLK
CLK period
25
-
ns
R202
t
CH/CL
CLK high/low time
5
-
ns
R203
t
FCLK/RCLK
CLK fall/rise time
-
3
ns
Synchronous Specifications
R301
t
AVCH/L
Address setup to CLK
9
-
ns
1
R302
t
VLCH/L
ADV# low setup to CLK
9
-
ns
R303
t
ELCH/L
CE# low setup to CLK
9
-
ns
R304
t
CHQV
/ t
CLQV
CLK to output valid
-
20
ns
R305
t
CHQX
Output hold from CLK
3
-
ns
1,5
R306
t
CHAX
Address hold from CLK
10
-
ns
1,4,5
R307
t
CHTV
CLK to WAIT valid
-
20
ns
1,5
R311
t
CHVL
CLK Valid to ADV# Setup
3
-
ns
1
R312
t
CHTX
WAIT Hold from CLK
3
-
ns
1,5
NOTES:
1.
See
Figure 13, “AC Input/Output Reference Waveform” on page 33
for timing measurements and max allowable input
slew rate.
OE# may be delayed by up to t
ELQV
– t
GLQV
after CE#’s falling edge without impact to t
ELQV
.
Sampled, not 100% tested.
Address hold in synchronous burst mode is t
or t
VHAX
, whichever timing specification is satisfied first.
Applies only to subsequent synchronous reads.
See your local Intel representative for designs requiring higher than 40 MHz synchronous operation.
2.
3.
4.
5.
6.
Table 17.
AC Read Specifications for 256/512-Mbit and 1-Gbit Densities (Sheet 2 of 2)
Num
Symbol
Parameter
Speed
Min
Max
Unit
Notes
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