參數(shù)資料
型號(hào)： PC33991DH
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 運(yùn)動(dòng)控制電子
英文描述： STEPPER MOTOR CONTROLLER, PDSO24
封裝： PLASTIC, SOIC-28
文件頁(yè)數(shù)： 5/36頁(yè)
文件大?。?/td> 660K
代理商： PC33991DH
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33991
13
TIMING DESCRIPTIONS AND DIAGRAMS
Figure 4. Single 16-bit Word SPI Communication
Figure 5. Multiple 16-bit Word SPI Communication
Data Input
The Input Shift register captures data at the falling edge of
the SCLK clock. The SCLK clock pulses exactly 16 times only
inside the transmission windows (CS in a logic [0] state). By the
time the CS signal goes to logic [1] again, the contents of the
Input Shift register are transferred to the appropriate internal
register, according to the address contained in bits 15-13. The
minimum time CS should be kept high depends on the internal
clock speed. That data is specified in the SPI Interface Timing
table. It must be long enough so the internal clock is able to
capture the data from the Input Shift register and transfer it to
the internal registers.
Data Output
At the first rising edge of the SCLK clock, with the CS at logic
[0], the contents of the status word register are transferred to
the Output Shift register. The first 16 bits clocked out are the
status bits. If data continues to clock in before the CS transitions
to a logic [1], the device begins to shift out the data previously
clocked in FIFO after the CS first transitioned to logic [0].
COMMUNICATION MEMORY MAPS
The 33991device is capable of interfacing directly with a
microcontroller, via the 16-bit SPI protocol described and
specified below. The device is controlled by the microprocessor
and reports back status information via the SPI. This section
provides a detailed description of all registers accessible via
serial interface. The various registers control the behavior of
this device.
A message is transmitted by the master starting with the
MSB (D15) and ending with the LSB (D0). Multiple messages
can be transmitted in succession to accommodate those
applications where daisy chaining is desirable, or to confirm
transmitted data, as long as the messages are all multiples of
16 bits. Data will transfer through daisy chained devices,
illustratedinFigure5. If anattempt is made tolatchina
message smaller than 16-bits wide, it is ignored.
The 33991uses six registers to con the device and control
the state of the four H-bridge outputs. Registers are addressed
via D15-D13 of the incoming SPI word. Refer to Table 2.
I n t e rnal r egist e rs a r e
load ed som e t im e
a f t er t his e dge
CS B
SI
SC L K
D1 5
D1
D2
D3
D4
D5
D6
D7
D8
D9
D1 4
D1 3
D1 2
D1 1
D1 0
OD 1 2
D0
OD1 3
OD 1 4
OD 1 5
OD 6
OD 7
OD8
OD 9
OD 1 0
OD 1 1
OD 1
OD 2
OD3
OD 4
OD 5
1.
S O is t ri- s t at ed w h en C S B is logic 1 .
NO T E S :
OD 0
SO
O u t put shif t regist e r is
lo aded here
SCLK
CS
SI
SO
cs
CS B
SI
SC L K
D1 5
D1 *
D2 *
D 13*
D 14*
D1 5 *
D0
D1
D1 4
D1 3
D2
D0 *
OD1 3
OD 1 4
OD 1 5
D1 4
D1 5
OD0
OD 1
OD 2
D1
D2
D1 3
1.
S O is t ri- s t at ed w hen C S B is logic 1 .
2.
D 1 5, D 1 4, D 1 3 , .. ., a n d D 0 re f er t o t h e f irst 16 bits o f da t a in t o t h e G D IC .
3.
D 1 5* , D 1 4 * , D 1 3*, . .. , a n d D 0 * re f e r t o t h e m ost re c ent e n t ry o f p ro gram dat a int o t he G D I C .
4.
O D 15, O D 14, O D 1 3 , . .. , and O D 0 r e f er t o t h e f irst 1 6 bit s of f a ult a nd s t at us d a t a out o f t h e G D I C .
NOT E S :
D0
SO
CS
SCLK
SI
SO
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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