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參數(shù)資料
| 型號： | PC33887DH/R2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | BRUSH DC MOTOR CONTROLLER, 6 A, PDSO20 |
| 封裝： | PLASTIC, HSOP-20 |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 412K |
| 代理商： | PC33887DH/R2 |
33887
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
10
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 5.0 V ≤ VPWR ≤ 28 V and -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
PWM Frequency (Note 18)
fPWM
–10–
kHz
Maximum Switching Frequency During Current Limit (Note 19)
fMAX
–
20
kHz
Output ON Delay (Note 20)
VPWR = 14 V
td(ON)
––
18
s
Output OFF Delay (Note 20)
VPWR = 14 V
td(OFF)
––
18
s
Output Latch-OFF Time
ta
15
20.5
26
s
Output Blanking Time
tb
12
16.5
21
s
Output Rise and Fall Time (Note 21)
VPWR = 14 V, IOUT = 3.0 A
tf, tr
2.0
5.0
8.0
s
Disable Delay Time (Note 22)
td(disable)
––
8.0
s
Overcurrent/Overtemperature Turn-OFF Time (Note 23)
tFAULT
–4.0
–
s
Power-ON Delay Time (Note 24)
tpod
–1.0
5.0
ms
Free-Wheeling Diode Reverse Recovery Time (Note 25)
trr
100
–
ns
Notes
18.
The outputs can be PWM controlled from an external source. This is typically done by holding one input high while applying a PWM pulse
train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching frequency. Refer
to Typical Switching Waveforms, Figure 8 through Figure 15.
19.
The Maximum Switching Frequency during Current Limit is internally implemented. The internal control produces a constant OFF-time PWM
of the output. The output load current effects the Maximum Switching Frequency.
20.
Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition
direction) of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from the midpoint of the input signal to the
90% point of the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from the midpoint of the input signal to the
10% point of the output response signal. See Figure 3.
21.
Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 4.
22.
Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tristate response. See Figure 3.
23.
Increasing output currents will become limited at 6.5 A. Hard shorts will breach the 6.5 A limit, forcing the output into an immediate tristate
latch-OFF. See Figure 6 and Figure 7. Output current limiting will cause junction temperatures to rise. A junction temperature above 160
°C
will cause the output current limit to progressively “fold-back” or decrease to 2.5 A typical at 175
°C where thermal latch-OFF will occur. See
Figure 5.
24.
This parameter has been characterized but is not production tested.
25.
Parameter is guaranteed by design but not production tested.
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| PC33887DW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
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