參數(shù)資料
型號(hào)： PC33879DWBR2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 運(yùn)動(dòng)控制電子
英文描述： BRUSH DC MOTOR CONTROLLER, 1 A, PDSO32
封裝： PLASTIC, SOIC-32
文件頁(yè)數(shù)： 8/20頁(yè)
文件大?。?/td> 747K
代理商： PC33879DWBR2
33879
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
16
DEVICE OPERATION
Power Supply
The 33879 device has been designed with ultra-low sleep
mode currents. The device may enter sleep mode via the EN
pin or the VDD pin. In the sleep mode (EN or VDD ≤ 0.8 V), the
current consumed by the VPWR pin is less than 5.0 A.
Placing the 33879 in sleep mode resets the internal registers
to the Power-ON Reset state. The reset state is defined as all
outputs off and Open Load Detect Current disabled.
To place the 33879 in the sleep mode, either command all
outputs off and apply logic low to the EN input pin or remove
power from the VDD supply pin. Prior to removing VDD from the
device, it is recommended all control inputs from the MCU are
low.
Paralleling of Outputs
Using MOSFETs as an output switch conveniently allows the
paralleling of outputs for increased current capability. RDS(ON) of
MOSFETs have an inherent positive temperature coefficient
providing balanced current sharing between outputs without
destructive operation. This mode of operation may be desirable
in the event the application requires lower power dissipation or
the added capability of switching higher currents. Performance
of parallel operation results in a corresponding decrease in
RDS(ON) while the output OFF Open Load Detect Currents and
the output current limits increase correspondingly. Paralleling
outputs from two or more different IC devices is possible but not
recommended.
Fault Logic Operation
Fault logic of the 33879 device has been greatly simplified
over other devices using SPI communications. As command
word one is being written into the shift register, a fault status
word is being simultaneously written out and received by the
MCU. Regardless of the configuration, with no outputs faulted
and Open Load Detect Current enabled, all status bits being
received by the MCU will be zero. When outputs are faulted (off
state open circuit or on state short circuit/overtemperature), the
status bits being received by the MCU will be one. The
distinction between open circuit fault and short/
overtemperature is completed via the command word. For
example, when a zero command bit is sent and a one fault is
received in the following word, the fault is open/short-to-battery
for high-side drive or open/short-to-ground for low-side drive. In
the same manner, when a one command bit is sent and a one
fault is received in the following word, the fault is a short-to-
ground/overtemperature for high-side drive or short-to-battery/
overtemperature for low-side drive. The timing between two
write words must be greater than 300
s to allow adequate time
to sense and report the proper fault status.
SPI Integrity Check
Checking the integrity of the SPI communication with the
initial power-up of the VDD and EN pins is recommended. After
initial system start-up or reset, the MCU will write one 32-bit
pattern to the 33879. The first 16 bits read by the MCU will be
8 logic [0]s followed by the fault status of the outputs. The
second 16 bits will be the same bit pattern sent by the MCU. By
the MCU receiving the same bit pattern it sent, bus integrity is
confirmed. Please note the second 16-bit pattern the MCU
sends to the device is the command word and will be
transferred to the outputs with rising edge of CS.
Important A SCLK pulse count strategy has been
implemented to ensure integrity of SPI communications. SPI
messages consisting of 16 SCLK pulses and multiples of
8 clock pulses thereafter will be acknowledged. SPI messages
consisting of other than 16 + multiples of 8 SCLK pulses will be
ignored by the device.
Overtemperature Fault
Overtemperature detect and shutdown circuits are
specifically incorporated for each individual output. The
shutdown following an overtemperature condition is
independent of the system clock or any other logic signal. Each
independent output shuts down at 155°C to 185°C. When an
output shuts down owing to an overtemperature fault, no other
outputs are affected. The MCU recognizes the fault by a one in
the fault status register. After the 33879 device has cooled
below the switch point temperature and 15°C hysteresis, the
output will activate unless told otherwise by the MCU via SPI to
shut down.
Overvoltage Fault
An overvoltage condition on the VPWR pin will cause the
device to shut down all outputs until the overvoltage condition
is removed. When the overvoltage condition is removed, the
outputs will resume their previous state. This device does not
detect an overvoltage on the VDD pin. The overvoltage
threshold on the VPWR pin is specified as 27 V to 30 V, with
1.0 V typical hysteresis. A VPWR overvoltage detect is global,
causing all outputs to be turned OFF.
Output OFF Open Load Fault
An output OFF open load fault is the detection and reporting
of an open load when the corresponding output is disabled
(input bit programmed to a logic low state). The Output OFF
Open Load fault is detected by comparing the drain-to-source
voltage of the specific MOSFET output to an internally
generated reference. Each output has one dedicated
comparator for this purpose.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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