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參數(shù)資料
| 型號(hào)： | PC33879DWBR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | BRUSH DC MOTOR CONTROLLER, 1 A, PDSO32 |
| 封裝： | PLASTIC, SOIC-32 |
| 文件頁數(shù)： | 20/20頁 |
| 文件大小： | 747K |
| 代理商： | PC33879DWBR2 |
ANALOG INTEGRATED CIRCUIT DEVICE DATA
33879
9
DIGITAL INTERFACE TIMING (Note 13)
Recommended Frequency of SPI Operation (Note 13)
fSPI
–4.0
–
MHz
Low State Duration on VDD for Reset
VDD ≤ 0.2 V
tRESET
–
100
–
ns
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
tLEAD
100
–
ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
tLAG
50
–
ns
DI to Falling Edge of SCLK (Required Setup Time)
tDI(su)
16
–
ns
Falling Edge of SCLK to DI (Required Hold Time)
tDI(HOLD)
20
–
ns
DI, CS, SCLK Signal Rise Time (Note 14)
tr(DI)
–5.0
–
ns
DI, CS, SCLK Signal Fall Time (Note 14)
tf(DI)
–5.0
–
ns
Time from Falling Edge of CS to DO Low Impedance (Note 15)
tDO(EN)
–
55
ns
Time from Rising Edge of CS to DO High Impedance (Note 16)
tDO(DIS)
–
55
ns
Time from Rising Edge of SCLK to DO Data Valid (Note 17)
tVALID
–25
55
ns
Notes
13.
This parameter is guaranteed by design. Production test equipment uses 4.16 MHz, 5.0 V SPI interface.
14.
Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
15.
Time required for output status data to be available for use at DO pin.
16.
Time required for output status data to be terminated at DO pin
17.
Time required to obtain valid data out from DO following the rise of SCLK.
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions of 3.1 V
≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C
Characteristic
Symbol
Min
Typ
Max
Units
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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