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參數(shù)資料
| 型號(hào)： | PC-414SRC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Last Time Buy Notice ? Board Products |
| 中文描述： | 最后一次購買的通知？板產(chǎn)品 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 197K |
| 代理商： | PC-414SRC |
PC-414
DATEL, Inc., Mansfield, MA 02048 (USA)
Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356
Email: sales@datel.com
Internet: www.datel.com
84
SPECIFICATIONS, CONTINUED
(Typical @ +25°C, dynamic conditions, unless noted)
A/D MEMORY
Architecture
Memory Capacity
First-In, First-Out (FIFO)
1024, 4096, or 16,384 A/D
samples. 64 K on request.
Programmable Interval
Timer Type
Functions
82C54
1. A/D sample count reached
2. A/D start rate (16 bit divisor)
3. SSH sample counter (414A)
3 to 65,536 samples. Drives
the Acquire flag/interrupt
gate for A/D start pulses.
Internal 8 MHz crystal clock
125, 250, or 500 KHz
Pacer Sample Counter
82C54 Clock Source
Scan Trigger Clock
Analog Trigger Input Range
[Note 5]
Analog Trigger Response
Analog Trigger Hysteresis
±10 V (not avail. 414D)
2 μs to set status flag
40 mV
Number of Channels
Function
(user-selectable)
[Note 5]
One
1. General purpose analog
output
2. Threshold comparator for
A/D trigger
12 bits
0 to +10 V, ±5 V and ±10 V
at 5 mA max.
±0.05% of FSR
Resolution
Output Voltage Range
(user-selectable)
Linearity
Settling Time
(10 V step)
Input Coding
(user-selectable)
5 microseconds to 0.05%
Same as A/D section
Architecture
I/O mapped, pluggable to
IBM-PC/AT, and compatibles.
Decodes eight 16-bit I/O
registers.
Decodes I/O address lines
A9 - A0
I/O transfer or host DMA,
software selectable
16 bits
1 channel, selectable on
channels 5, 6, or 7, set by
software
FIFO full, half full, not empty,
scan acquire flag (sample
count reached)
Board reset, FIFO flags,
interrupt select and status,
DMA select and status, trigger
source, timer control and
period, sample count load,
parallel outport enable, A/D
enable, MUX auto-sequence
I/O Mapping
Data Transfer
Data Bus
Direct Memory Access
DMA Request Conditions
(software selectable)
Control/Status Functions
Number of Interrupts
(software selectable)
1 interrupt, software
selectable on level 7, 9 thru
11, or 15.
Scan acquire flag (sample
count), FIFO full or half full,
DMA terminal count from bus.
Bus Interrupt Sources
Outport Type
16 data output lines, TTL
levels from A/D FIFO.
Includes handshake signals
and FIFO flags. The outport
does not provide addressing.
Asynchoronous master to
external slave receiver. 4
modes are included, offering
internal/external clocking (to
10 MHz), synchronous/
asynchronous handshaking.
Sequencing is compatible
with DT Connect
.
24 mA out, 1.6 mA in. The
data outputs may be tri-stated
for shared bus connection.
2-row 26-pin header type
mounted on board interior.
0.100” pin spacing suitable
for flat cable. Pinout is
compatible with DT Connect
and existing 414 format.
4 MHz max. Data may be
transferred up to 10 MHz
with external clocking.
Operating Modes
Parallel Port Loading
Parallel Port Connector
Port Data Rate
Connector
Dual row, 26-pin header
mounted on board interior.
Uses 0.100” pin spacing
suitable for flat cable.
Includes +5 Vdc and digital
ground connections.
8 digital outputs, 8 digital
inputs (unlatched)
Buffered, TTL levels.
10 output loads.
50 ns max. after write operation
Configuration
Levels
Outport Settling Time
Analog Section Modularity
The MUX-S/H-A/D module is
socketed for function
interchange.
Offset and gain per channel
for SSH on PC-414F, G, H,
K, M, N, and P. A single
offset and gain pot is
provided on PC-414B, D,
and E. Recommended
recalibration interval is 90
days in stable conditions.
Four SMA miniature coaxial,
mounted on rear slot. [Note 8]
Analog Section Adjustments
Analog Input Connectors
TRIGGER CONTROL
PARALLEL DATA PORT
DIGITAL I/O PORT
MISCELLANEOUS
ANALOG OUTPUT
ISA BUS INTERFACE
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