參數(shù)資料
型號: PC-414SRC
廠商: Electronic Theatre Controls, Inc.
英文描述: Last Time Buy Notice ? Board Products
中文描述: 最后一次購買的通知?板產品
文件頁數(shù): 10/14頁
文件大?。?/td> 197K
代理商: PC-414SRC
PC-414
DATEL, Inc., Mansfield, MA 02048 (USA)
Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356
Email: sales@datel.com
Internet: www.datel.com
86
I/O Register Mapping
The base address may be selected anywhere up to 3F0h on
16-byte boundaries.
I/O Address
(hex)
Direction
Description
Base + 0
Base + 0
Base + 2
Write
Read
Write
Command Register
Status Register
Channel Address/Digital
Output [Note 12]
Digital Input Register
[Note 12]
D/A Data Register
FIFO Reset Register
FIFO A/D Data Register
Counter #0 (82C54)
Counter #1 (82C54)
Counter #2 (82C54)
Control Register (82C54)
Base + 2
Read
Base + 4
Base + 6
Base + 6
Base +8
Base + 0Ah
Base + 0Ch
Base + 0Eh
Write
Write
Read
Read/Write
Read/Write
Read/Write
Read/Write
Transfer Speeds
ISA bus transfer rates are host-dependent and should be
determined by testing. For example, a Compaq computer
achieved 800 nanoseconds instantaneous sample-to-sample
timing to base memory using the REP INSW instruction. A
faster CPU will not increase the ISA bus speed. To optimize
throughput, disable all possible interrupts. For higher speed
continuous (non-stop) A/D sampling, consider using a parallel
port.
Figure 4. PC-414 Timing DIagram
Internal or external trigger rate
TRIGGER
A/D
START
CONVERT
END OF
SCAN*
(Internal
(Signal)
ACQUIRE
FLAG
Maskable Interrupt
and Status
0
1
2
3
Fixed or sequential channel addressing up to
64k samples per trigger
SSH (Internal)
[BASE + 0 bit 2 = 1]
(414A only)
HOLD
SAMPLE
Internal or external start rate
Figure 3. Array Preprocessing
Analog
Inputs
Binary A/D Data
Parallel
Port
DSP Arrays
PC/AT Bus
Graphics
Display
Mass Storage
PC-414
MUX
A/D
FIFO
MEM
Array
Processor
Board
CPU
Disk
Controller
Display
Controller
See model PC-414COM
using a DSP COMM
port interface.
FIFO Data Format
A/D data is delivered as a stream from the FIFO memory. For
multichannel inputs, this means that data is multiplexed. For
example, for 4-channel inputs, the output channel sequence is
0, 1, 2, 3, 0, 1, . . . Some applications may need this data de-
multiplexed by software so that each channel’s data is placed
in its own separate buffer.
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