
PC-414
DATEL, Inc., Mansfield, MA 02048 (USA)
Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356
Email: sales@datel.com
Internet: www.datel.com
83
FUNCTIONAL SPECIFICATIONS
(Typical at +25°C, dynamic conditions, gain = 1, unless noted)
ANALOG INPUTS
Number of Channels
Input Configuration
(non-isolated) [Note 19]
Full Scale Input Ranges
(user-selectable) (gain = 1)
[Notes 1 & 16]
Input Overvoltage
(no damage, power on)
Overvoltage Recovery
Time,
maximum
Common Mode Voltage
Range,
maximum
Input Impedance
[Notes 6 &10]
Acquisition Time
(FSR step to 0.01% of FSR, max.)
Aperture Delay
Aperture Delay Uncertainty
Resolution
Conversion Period
Integral Non-linearity
(LSB of FSR)
Differential Non-linearity
(LSB of FSR)
Full Scale Temperature
Coefficient
(LSB per °C)
Zero or Offset
Temperature Coefficient
(LSB per °C)
Throughput to FIFO
(single channel, gain = 1)
Throughput to FIFO
(sequential channels,
gain = 1)
Total Harmonic Distortion
[Note 3]
PC-414L
16 Simultaneous
A/D’s
Single Ended
±5 V, ±10 V,
(user selectable)
[Note 13]
±15 V
—
—
8 k
400 ns
—
—
12 bits
2 μs [Note 12]
±2
±1
[Note 10]
[Note 10]
400 kHz
190 kHz/chan.
-75 dB
PC-414M
4 Simultaneous
A/D’s
Single Ended
±10 V
±12 V
—
—
10 M
—
—
—
16 bits
5 μs [Note 12]
±4
±3
±1
±1
200 kHz
200 kHz/chan.
-83 dB
PC-414P
4 Simultaneous
A/D’s
Single Ended
±2.5 V or
0 to +5 V
(user selectable)
±7 V
—
—
1000
—
—
—
14 bits
400 ns [Note 12]
±3
±1.5
±0.5
±0.5
3 MHz* min.
2.5 MHz/chan.
-75 dB
PC-414N
2 Simultaneous
A/D’s
Single Ended
±2.5 V
±15V
—
—
10 M
or 50
35 ns
±10 ns
5 ps
14 bits
200 ns [Note 12]
±1
±1
±0.5
±0.5
5 MHz
5 MHz/chan.
-75 dB
SAMPLE/HOLD
A/D CONVERTER
SYSTEM DYNAMIC PERFORMANCE
[Note 2]
SYSTEM DC CHARACTERISTICS
[Note 7]
* The sample rate to published specifications is 3 MHz. The A/D is functional to 5 MHz. Valid data output per channel is delayed
by 4 samples after the start of the sample clock. Please make note of this for products such as the PC-414P, PC-430P, and
DVME-614P which use non-continuous A/D sampling. Data output is pipelined meaning that the first four samples per channel
should be discarded. For all 4 channels, discard 16 samples. The design is intended for semi-continuous sampling of wideband
signals and is less suitable for low speed data acquisition. Approximately 5 dB SFDR improvement can be achieved by directly
connecting an external A/D sample clock. Contact DATEL for details.