參數(shù)資料
型號(hào)： PA28F008SC-120
廠商： INTEL CORP
元件分類(lèi)： PROM
英文描述： BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT
中文描述： 1M X 8 FLASH 3.3V PROM, 120 ns, PDSO44
封裝： 13.30 X 28.20 MM, PLASTIC, SOP-44
文件頁(yè)數(shù)： 14/33頁(yè)
文件大?。?/td> 466K
代理商： PA28F008SC-120
28F008SA
Byte Write Setup/Write Commands
(40H or 10H)
Byte write is executed by a two-command sequence.
The Byte Write Setup command (40H or 10H) is writ-
ten to the Command User Interface, followed by a
second write specifying the address and data
(latched on the rising edge of WE
Y
) to be written.
The WSM then takes over, controlling the byte write
and write verify algorithms internally. After the two-
command byte write sequence is written to it, the
28F008SA automatically outputs Status Register
data when read (see Figure 7; Byte Write Flowchart).
The CPU can detect the completion of the byte write
event by analyzing the output of the RY/BY
Y
pin, or
the WSM Status bit of the Status Register. Only the
Read Status Register command is valid while byte
write is active.
When byte write is complete, the Byte Write Status
bit should be checked. If byte write error is detected,
the Status Register should be cleared. The internal
WSM verify only detects errors for ‘‘1’’s that do not
successfully write to ‘‘0’’s. The Command User In-
terface remains in Read Status Register mode until
further commands are issued to it. If byte write is
attempted while V
PP
e
V
PPL
, the V
PP
Status bit will
be set to ‘‘1’’. Byte write attempts while V
PPL
k
V
PP
k
V
PPH
produce spurious results and should not be
attempted.
EXTENDED BLOCK ERASE/BYTE
WRITE CYCLING
Intel has designed extended cycling capability into
its
ETOX
flash
memory
28F008SA is designed for 100,000 byte write/block
erase cycles on each of the sixteen 64-Kbyte
blocks. Low electric fields, advanced oxides and
minimal oxide area per cell subjected to the tunnel-
ing electric field combine to greatly reduce oxide
stress and the probability of failure. A 20-Mbyte sol-
id-state drive using an array of 28F008SAs has a
MTBF (Mean Time Between Failure) of 33.3 million
hours
(1)
, over 600 times more reliable than equiva-
lent rotating disk technology.
technologies.
The
AUTOMATED BYTE WRITE
The 28F008SA integrates the Quick-Pulse program-
ming algorithm of prior Intel Flash devices on-chip,
using the Command User Interface, Status Register
and Write State Machine (WSM). On-chip integration
dramatically simplifies system software and provides
processor interface timings to the Command User
Interface and Status Register. WSM operation, inter-
nal verify and V
PP
high voltage presence are moni-
tored and reported via the RY/BY
Y
output and ap-
propriate Status Register bits. Figure 7 shows a
system software flowchart for device byte write. The
entire sequence is performed with V
PP
at V
PPH
. Byte
write abort occurs when RP
Y
transitions to V
IL
, or
V
PP
drops to V
PPL
. Although the WSM is halted,
byte data is partially written at the location where
byte write was aborted. Block erasure, or a repeat of
byte write, is required to initialize this data to a
known value.
AUTOMATED BLOCK ERASE
As above, the Quick-Erase algorithm of prior Intel
Flash devices is now implemented internally, includ-
ing all preconditioning of block data. WSM opera-
tion, erase success and V
PP
high voltage presence
are monitored and reported through RY/BY
Y
and
the Status Register. Additionally, if a command other
than Erase Confirm is written to the device following
Erase Setup, both the Erase Status and Byte Write
Status bits will be set to ‘‘1’’s. When issuing the
Erase Setup and Erase Confirm commands, they
should be written to an address within the address
range of the block to be erased. Figure 8 shows a
system software flowchart for block erase.
Erase typically takes 1.6 seconds per block. The
Erase Suspend/Erase Resume command sequence
allows suspension of this erase operation to read
data from a block other than that in which erase is
being performed. A system software flowchart is
shown in Figure 9.
The entire sequence is performed with V
PP
at V
PPH
.
Abort occurs when RP
Y
transitions to V
IL
or V
PP
falls to V
PPL
, while erase is in progress. Block data is
partially erased by this operation, and a repeat of
erase is required to obtain a fully erased block.
DESIGN CONSIDERATIONS
Three-Line Output Control
The 28F008SA will often be used in large memory
arrays. Intel provides three control inputs to accom-
modate multiple memory connections. Three-line
control provides for:
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will
not occur
To efficiently use these control inputs, an address
decoder should enable CE
Y
, while OE
Y
should be
connected to all memory devices and the system’s
READ
Y
control line. This assures that only selected
memory devices have active outputs while deselect-
ed memory devices are in Standby Mode. RP
Y
should be connected to the system Powergood sig-
nal to prevent unintended writes during system pow-
er transitions. Powergood should also toggle during
system reset.
(1)
Assumptions: 10-Kbyte file written every 10 minutes. (20-Mbyte array)/(10-Kbyte file)
e
2,000 file writes before erase required.
(2000 files writes/erase)
c
(100,000 cycles per 28F008SA block)
e
200 million file writes.
(200
c
10
6
file writes)
c
(10 min/write)
c
(1 hr/60 min)
e
33.3
c
10
6
MTBF
.
14
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