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參數(shù)資料
| 型號： | PA28F008SA-85 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 8-MBIT (1-MBIT x 8) FlashFileTM MEMORY |
| 中文描述： | 1M X 8 FLASH 12V PROM, 85 ns, PDSO44 |
| 封裝： | 0.525 X 1.110 INCH, PLASTIC, SOP-44 |
| 文件頁數(shù)： | 11/33頁 |
| 文件大?。?/td> | 466K |
| 代理商： | PA28F008SA-85 |
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28F008SA
Deep Power-Down
The 28F008SA offers a deep power-down feature,
entered when RP
Y
is at V
IL
. Current draw thru V
CC
is 0.20
m
A typical in deep power-down mode, with
current draw through V
PP
typically 0.1
m
A. During
read modes, RP
Y
-low deselects the memory,
places output drivers in a high-impedence state and
turns off all internal circuits. The 28F008SA requires
time t
PHQV
(see AC Characteristics-Read-Only Op-
erations) after return from powerdown until initial
memory access outputs are valid. After this wakeup
interval, normal operation is restored. The Com-
mand User Interface is reset to Read Array, and the
upper 5 bits of the Status Register are cleared to
value 10000, upon return to normal operation.
During block erase or byte write modes, RP
Y
low
will abort either operation. Memory contents of the
block being altered are no longer valid as the data
will be partially written or erased. Time t
PHWL
after
RP
Y
goes to logic-high (V
IH
) is required before an-
other command can be written.
This use of RP
Y
during system reset is important
with automated write/erase devices. When the sys-
tem comes out of reset it expects to read from the
flash memory. Automated flash memories provide
status information when accessed during write/
erase modes. If a CPU reset occurs with no flash
memory reset, proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data. Intel’s
Flash Memories allow proper CPU initialization fol-
lowing a system reset through the use of the RP
Y
input. In this application RP
Y
is controlled by the
same RESET
Y
signal that resets the system CPU.
Intelligent Identifier Operation
The intelligent identifier operation outputs the manu-
facturer code, 89H; and the device code, A2H for
the 28F008SA. The system CPU can then automati-
cally match the device with its proper block erase
and byte write algorithms.
The manufacturer- and device-codes are read via
the Command User Interface. Following a write of
90H to the Command User Interface, a read from
address location 00000H outputs the manufacturer
code (89H). A read from address 00001H outputs
the device code (A2H). It is not necessary to have
high voltage applied to V
PP
to read the intelligent
identifiers from the Command User Interface.
Table 3. Command Definitions
Command
Cycles
Req’d
Bus
Notes
First Bus Cycle
Second Bus Cycle
Operation Address Data Operation Address Data
Read Array/Reset
1
1
Write
X
FFH
Intelligent Identifier
3
2, 3, 4
Write
X
90H
Read
IA
IID
Read Status Register
2
3
Write
X
70H
Read
X
SRD
Clear Status Register
1
Write
X
50H
Erase Setup/Erase Confirm
2
2
Write
BA
20H
Write
BA
D0H
Erase Suspend/Erase Resume
2
Write
X
B0H
Write
X
D0H
Byte Write Setup/Write
2
2, 3, 5
Write
WA
40H
Write
WA
WD
Alternate Byte Write Setup/Write
2
2, 3, 5
Write
WA
10H
Write
WA
WD
NOTES:
1. Bus operations are defined in Table 2.
2. IA
e
Identifier Address: 00H for manufacturer code, 01H for device code.
BA
e
Address within the block being erased.
WA
e
Address of memory location to be written.
3. SRD
e
Data read from Status Register. See Table 4 for a description of the Status Register bits.
WD
e
Data to be written at location WA. Data is latched on the rising edge of WE
Y
.
IID
e
Data read from Intelligent Identifiers.
4. Following the Intelligent Identifier command, two read operations access manufacture and device codes.
5. Either 40H or 10H are recognized by the WSM as the Byte Write Setup command.
6. Commands other than those shown above are reserved by Intel for future device implementations and should not be
used.
11
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