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| 型號： | P8xCL580HFH |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC |
| 中文描述： | 低電壓8 - UART的，位微控制器的I2C總線和ADC |
| 文件頁數(shù)： | 23/80頁 |
| 文件大?。?/td> | 366K |
| 代理商： | P8XCL580HFH |
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1997 Mar 14
23
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I
2
C-bus and ADC
P80CL580; P83CL580
13 ANALOG-TO-DIGITAL CONVERTER (ADC)
The analog input circuitry consists of a 4-bit analog
multiplexer and an ADC with 8-bit resolution. The analog
reference voltage (V
ref(p)(A)
) and analog ground (V
SSA
) are
connected via separate input pins. The conversion is
selectable from 24 machine cycles (24
μ
s at
f
osc
= 12 MHz) to 48 machine cycles. The functional
diagram of the ADC is shown in Fig. 14.
The ADC is controlled using the ADC Control Register
(ADCON). Input channels are selected by the analog
multiplexer via the ADCON register bits AADR0 and
AADR1. The completion of the 8-bit ADC conversion is
flagged by ADCI in the ADCON register and the result is
stored in the Special Function Register ADCH (address
C5H).
An ADC conversion in progress is unaffected by an
external software ADC start.
The result of a completed conversion remains unaffected
provided ADCI = 1. While ADCS = 1 or ADCI = 1, a new
ADC start will be blocked and consequently lost.
An ADC conversion already in progress is aborted when
the Power-down mode is entered. The result of a
completed conversion (ADCI = 1) remains unaffected
when entering the Idle or Power-down mode.
The analog-to-digital conversion can be started in 3 ways:
Start in operating mode, continue in operating mode
Start in operating mode, by setting the ADCS bit, then go
to Idle mode
Set the ADEX bit, go to the Idle mode and start
conversion externally via the STADC pin.
For the three cases mentioned above the internal flag
ADCI is set upon completion of the conversion.
Fig.14 Functional diagram of analog input.
handbook, full pagewidth
MGC751
ADC0
ANALOG INPUT
MULTIPLEXER
8-BIT ADC
(succesive approximation)
ADCON
(1)
START
END
1
2
3
4
5
6
7
0
1
2
3
4
5
6
-
0
STADC
ADEX
Vref(p)(A)
VSSA
+
ADCH
INTERNAL BUS
ADC1
ADC2
ADC3
(1) For the descriptions of ADCON bits see Table 10.
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