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| 型號： | P89V52X2FN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 38/57頁 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 8K 40-DIP |
| 產(chǎn)品培訓模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標準包裝： | 216 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | POR |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 192 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
| 配用： | 622-1017-ND - BOARD 44-ZIF PLCC SOCKET 622-1012-ND - BOARD FOR P89V52X2 44-TQFP 622-1008-ND - BOARD FOR LPC9103 10-HVSON |
| 其它名稱： | 568-4251-5 935282526112 P89V52X2FN |
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P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
43 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
[1]
This parameter is measured only for initial qualication and after a design or process change that could affect this parameter.
[2]
Under steady state (non-transient) conditions, IOL must be externally limited as follows:
a) Maximum IOL per 8-bit port: 26 mA
b) Maximum IOL total for all outputs: 71 mA
c) If IOL exceeds the test condition, VOH may exceed the related specication. Pins are not guaranteed to sink current greater than the
listed test conditions.
[3]
Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOL of ALE and Ports 1 and 3. The noise due
to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to
qualify ALE with a Schmitt trigger, or use an address latch with a Schmitt trigger STROBE input.
[4]
Load capacitance for Port 0, ALE and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
[5]
Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VDD 0.7 specication when
the address bits are stabilizing.
[6]
Pins of Ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VI is approximately 2 V.
[7]
Pin capacitance is characterized but not tested. EA = 25 pF (max).
Rpd
pull-down
resistance
on pin RST
40
-
225
k
Ciss
input capacitance
@ 1 MHz, Tamb =25 °C,
VI =0V
[7] -
-
15
pF
IDD(oper)
operating supply
current
fosc = 12 MHz
-
3
mA
fosc = 40 MHz
-
7
mA
IDD(idle)
Idle mode supply
current
fosc = 12 MHz
-
1.7
mA
fosc = 40 MHz
-
3
mA
IDD(pd)
Power-down mode
supply current
minimum VDD =2V
-
15
A
Table 44.
Static characteristics …continued
Tamb = 40 °C to +85 °C; VDD = 2.7 V to 5.5 V; VSS =0V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
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