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參數(shù)資料
| 型號(hào)： | P89V52X2FN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 28/57頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 8K 40-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 216 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | POR |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大小： | 192 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
| 配用： | 622-1017-ND - BOARD 44-ZIF PLCC SOCKET 622-1012-ND - BOARD FOR P89V52X2 44-TQFP 622-1008-ND - BOARD FOR LPC9103 10-HVSON |
| 其它名稱： | 568-4251-5 935282526112 P89V52X2FN |
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P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
34 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
The data EEPROM must be mapped into the code memory address space in order to
read, erase, or program the data EEPROM. The memory is read using the MOVC
instruction.
6.13.1 Features
ICP with industry-standard commercial programmers
IAP-Lite allows individual and multiple bytes of data EEPROM to be programmed
under control of the end application.
Programming and erase over the full operating voltage range
Programming/Erase using ICP or IAP-Lite
Program or erases requires 2 ms, 4 ms, or 6 ms, depending on the operation
Programmable security for the data in each page
> 100000 typical erase/program cycles for each byte
Data EEPROM mapped into code space for quick MOVC reading
6.13.2 Register interface
Erasing, programming, and mapping operations are performed in the application under
the control of the microcontroller’s rmware using four SFRs and an internal 64-byte ‘page
register’. These SFRs are:
FMCON (Flash Control Register). When read, this is the status register. When written,
this is a command register. Note that the status bits are cleared to logic 0s when the
command is written.
FMADRL, FMADRH (Flash memory address low, Flash memory address high). Used
to specify the byte address within the page register or specify the page within user
code memory (for programming, erase, and reading the data EEPROM is mapped
into the user address space (see Table 32).
FMDATA (Flash Data Register). Accepts data to be loaded into the page register.
Data is read by mapping the data EEPROM into the code memory space and using the
MOVC instruction.
6.13.3 Mapping the data EEPROM into code space
In order to read, erase, or program the data EEPROM must be mapped into the code
memory address space. This is accomplished by writing the MAP command (09H) to
FMCON. The data EEPROM may be unmapped by writing the UNMAP command (0AH)
to FMCON. The mapping of the data EEPROM pages into code memory space is shown
in Table 32.
6.13.4 Reading the data EEPROM
Reading the data EEPROM can be achieved by performing the following sequence:
Table 32.
Data EEPROM page addresses
Data EEPROM page
Start address End address
0
FF00H
FF3FH
1
FF40H
FF7FH
2
FF80H
FFBFH
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| P89V660 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI |
| P89V660_08 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI |
| P89V660_0811 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI |
| P89V660FA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI |
| P89V660FA,512 | 功能描述:8位微控制器 -MCU 80C51 16K FL / 512 R RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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