參數(shù)資料
型號(hào): P89V51RC2FA,512
廠商: NXP Semiconductors
文件頁(yè)數(shù): 44/80頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 32K 44-PLCC
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 26
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 706 (CN2011-ZH PDF)
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱(chēng): 568-2428-5
935277727512
P89V51RC2FA
P89V51RB2_RC2_RD2_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 November 2009
49 of 80
NXP Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Table 37.
CMOD - PCA counter mode register (address D9H) count pulse select
CPS1
CPS0
Select PCA input
0
0 Internal clock, fosc / 6
0
1
1 Internal clock, fosc / 2
1
0
2 Timer 0 overow
1
3 External clock at ECI/P1.2 pin (max rate = fosc / 4)
Table 38.
CCON - PCA counter control register (address 0D8H) bit allocation
Bit addressable; Reset value: 00H
Bit
7
6
5
4
3
2
1
0
Symbol
CF
CR
-
CCF4
CCF3
CCF2
CCF1
CCF0
Table 39.
CCON - PCA counter control register (address 0D8H) bit description
Bit
Symbol
Description
7
CF
PCA counter overow ag. Set by hardware when the counter rolls
over. CF ags an interrupt if bit ECF in CMOD is set. CF may be set by
either hardware or software but can only be cleared by software.
6
CR
PCA counter run control bit. Set by software to turn the PCA counter
on. Must be cleared by software to turn the PCA counter off.
5
-
Reserved for future use. Should be set to ‘0’ by user programs.
4
CCF4
PCA Module 4 Interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
3
CCF3
PCA Module 3 Interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
2
CCF2
PCA Module 2 Interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
1
CCF1
PCA Module 1 Interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
0
CCF0
PCA Module 0 Interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
Table 40.
CCAPMn - PCA modules compare/capture register (address CCAPM0 0DAH,
CCAPM1 0DBH, CCAPM2 0DCH, CCAPM3 0DDH, CCAPM4 0DEH) bit allocation
Not bit addressable; Reset value: 00H
Bit
7
6
5
4
3
2
1
0
Symbol
-
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
Table 41.
CCAPMn - PCA modules compare/capture register (address CCAPM0 0DAH,
CCAPM1 0DBH, CCAPM2 0DCH, CCAPM3 0DDH, CCAPM4 0DEH) bit description
Bit
Symbol
Description
7
-
Reserved for future use. Should be set to ‘0’ by user programs.
6
ECOMn
Enable Comparator. ECOMn = 1 enables the comparator function.
5
CAPPn
Capture Positive, CAPPn = 1 enables positive edge capture.
4
CAPNn
Capture Negative, CAPNn = 1 enables negative edge capture.
3
MATn
Match. When MATn = 1 a match of the PCA counter with this module’s
compare/capture register causes the CCFn bit in CCON to be set,
agging an interrupt.
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