參數(shù)資料
型號: P89V51RC2FA,512
廠商: NXP Semiconductors
文件頁數(shù): 14/80頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 32K 44-PLCC
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 26
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱: 568-2428-5
935277727512
P89V51RC2FA
P89V51RB2_RC2_RD2_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 November 2009
21 of 80
NXP Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
A chip-erase operation can be performed using a commercially available parallel
programer. This operation will erase the contents of this boot block and it will be
necessary for the user to reprogram this boot block (block 1) with the NXP-provided
ISP/IAP code in order to use the ISP or IAP capabilities of this device. Go to
http://www.nxp.com/support for questions or to obtain the hex le for this device.
6.3.3 ISP
ISP is performed without removing the microcontroller from the system. The ISP facility
consists of a series of internal hardware resources coupled with internal rmware to
facilitate remote programming of the P89V51RB2/RC2/RD2 through the serial port. This
rmware is provided by NXP and embedded within each P89V51RB2/RC2/RD2 device.
The NXP ISP facility has made in-circuit programming in an embedded application
possible with a minimum of additional expense in components and circuit board area. The
ISP function uses ve pins (VDD, VSS, TXD, RXD, and RST). Only a small connector
needs to be available to interface your application to an external circuit in order to use this
feature.
6.3.4 Using ISP
The ISP feature allows for a wide range of baud rates to be used in your application,
independent of the oscillator frequency. It is also adaptable to a wide range of oscillator
frequencies. This is accomplished by measuring the bit-time of a single bit in a received
character. This information is then used to program the baud rate in terms of timer counts
based on the oscillator frequency. The ISP feature requires that an initial character (an
uppercase U) be sent to the P89V51RB2/RC2/RD2 to establish the baud rate. The ISP
rmware provides auto-echo of received characters. Once baud rate initialization has
been performed, the ISP rmware will only accept Intel Hex-type records. Intel Hex
records consist of ASCII characters used to represent hexadecimal values and are
summarized below:
:NNAAAARRDD..DDCC<crlf>
In the Intel Hex record, the ‘NN’ represents the number of data bytes in the record. The
P89V51RB2/RC2/RD2 will accept up to 32 data bytes. The ‘AAAA’ string represents the
address of the rst byte in the record. If there are zero bytes in the record, this eld is often
set to 0000. The ‘RR’ string indicates the record type. A record type of ‘00’ is a data
record. A record type of ‘01’ indicates the end-of-le mark. In this application, additional
record types will be added to indicate either commands or data for the ISP facility.
The maximum number of data bytes in a record is limited to 32 (decimal). ISP commands
are summarized in Table 12. As a record is received by the P89V51RB2/RC2/RD2, the
information in the record is stored internally and a checksum calculation is performed. The
operation indicated by the record type is not performed until the entire record has been
received. Should an error occur in the checksum, the P89V51RB2/RC2/RD2 will send an
‘X’ out the serial port indicating a checksum error. If the checksum calculation is found to
match the checksum in the record, then the command will be executed. In most cases,
successful reception of the record will be indicated by transmitting a ‘.’ character out the
serial port.
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