參數(shù)資料
型號: P89V51RB2BBC,557
廠商: NXP Semiconductors
文件頁數(shù): 77/80頁
文件大?。?/td> 0K
描述: IC 80C51 MCU 1024 RAM 44TQFP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 800
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-TQFP
包裝: 托盤
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
其它名稱: 935277723557
P89V51RB2BBC
P89V51RB2BBC-ND
2009-2011 Microchip Technology Inc.
DS39960D-page 79
PIC18F87K22 FAMILY
TABLE 5-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET
Instruction,
Stack Resets,
CM Resets
Wake-up via WDT
or Interrupt
TOSU
PIC18F6XK22 PIC18F8XK22
- - - 0 0000
---0 uuuu(1)
TOSH
PIC18F6XK22 PIC18F8XK22
0000 0000
uuuu uuuu(1)
TOSL
PIC18F6XK22 PIC18F8XK22
0000 0000
uuuu uuuu(1)
STKPTR
PIC18F6XK22 PIC18F8XK22
00- 0 0000
uu- 0 0000
uu-u uuuu(1)
PCLATU
PIC18F6XK22 PIC18F8XK22
- - - 0 0000
---u uuuu
PCLATH
PIC18F6XK22 PIC18F8XK22
0000 0000
uuuu uuuu
PCL
PIC18F6XK22 PIC18F8XK22
0000 0000
PC + 2(2)
TBLPTRU
PIC18F6XK22 PIC18F8XK22
- - 00 0000
--uu uuuu
TBLPTRH
PIC18F6XK22 PIC18F8XK22
0000 0000
uuuu uuuu
TBLPTRL
PIC18F6XK22 PIC18F8XK22
0000 0000
uuuu uuuu
TABLAT
PIC18F6XK22 PIC18F8XK22
0000 0000
uuuu uuuu
PRODH
PIC18F6XK22 PIC18F8XK22
xxxx xxxx
uuuu uuuu
PRODL
PIC18F6XK22 PIC18F8XK22
xxxx xxxx
uuuu uuuu
INTCON
PIC18F6XK22 PIC18F8XK22
0000 000x
0000 000u
uuuu uuuu
INTCON2
PIC18F6XK22 PIC18F8XK22
1111 1111
uuuu uuuu(3)
INTCON3
PIC18F6XK22 PIC18F8XK22
1100 0000
uuuu uuuu
INDF0
PIC18F6XK22 PIC18F8XK22
N/A
POSTINC0
PIC18F6XK22 PIC18F8XK22
N/A
POSTDEC0
PIC18F6XK22 PIC18F8XK22
N/A
PREINC0
PIC18F6XK22 PIC18F8XK22
N/A
PLUSW0
PIC18F6XK22 PIC18F8XK22
N/A
FSR0H
PIC18F6XK22 PIC18F8XK22
- - - - 0000
---- uuuu
FSR0L
PIC18F6XK22 PIC18F8XK22
xxxx xxxx
uuuu uuuu
WREG
PIC18F6XK22 PIC18F8XK22
xxxx xxxx
uuuu uuuu
INDF1
PIC18F6XK22 PIC18F8XK22
N/A
POSTINC1
PIC18F6XK22 PIC18F8XK22
N/A
POSTDEC1
PIC18F6XK22 PIC18F8XK22
N/A
PREINC1
PIC18F6XK22 PIC18F8XK22
N/A
PLUSW1
PIC18F6XK22 PIC18F8XK22
N/A
FSR1H
PIC18F6XK22 PIC18F8XK22
- - - - 0000
---- uuuu
FSR1L
PIC18F6XK22 PIC18F8XK22
xxxx xxxx
uuuu uuuu
BSR
PIC18F6XK22 PIC18F8XK22
- - - - 0000
---- uuuu
Legend:
u
= unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1:
When the wake-up is due to an interrupt, and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
2:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3:
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4:
See Table 5-1 for Reset value for specific condition.
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