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參數(shù)資料
| 型號： | P89V51RB2BBC,557 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 74/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU 1024 RAM 44TQFP |
| 產(chǎn)品培訓模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標準包裝： | 800 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 16KB（16K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
| 配用： | 622-1017-ND - BOARD 44-ZIF PLCC SOCKET |
| 其它名稱： | 935277723557 P89V51RB2BBC P89V51RB2BBC-ND |
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PIC18F87K22 FAMILY
DS39960D-page 76
2009-2011 Microchip Technology Inc.
5.5
Configuration Mismatch (CM)
The Configuration Mismatch (CM) Reset is designed to
detect, and attempt to recover from, random, memory
corrupting events. These include Electrostatic Discharge
(ESD) events that can cause widespread, single bit
changes throughout the device and result in catastrophic
failure.
In PIC18F87K22 family Flash devices, the device
Configuration registers (located in the configuration
memory space) are continuously monitored during
operation by comparing their values to complimentary
shadow registers. If a mismatch is detected between
the two sets of registers, a CM Reset automatically
occurs. These events are captured by the CM bit
(RCON<5>). The state of the bit is set to ‘0’ whenever
a CM event occurs and does not change for any other
Reset event.
A CM Reset behaves similarly to a Master Clear Reset,
RESET
instruction, WDT time-out or Stack Event Reset.
As with all hard and power Reset events, the device
Configuration Words are reloaded from the Flash
Configuration Words in program memory as the device
restarts.
5.6
Power-up Timer (PWRT)
PIC18F87K22 family devices incorporate an on-chip
Power-up Timer (PWRT) to help regulate the Power-on
Reset process. The PWRT is enabled by setting the
PWRTEN bit (CONFIG2L<0>). The main function is to
ensure that the device voltage is stable before code is
executed.
The Power-up Timer (PWRT) of the PIC18F87K22
family devices is a 13-bit counter that uses the
LF-INTOSC source as the clock input. This yields an
approximate time interval of 2,048 x 32
s= 66 ms.
While the PWRT is counting, the device is held in
Reset.
The power-up time delay depends on the LF-INTOSC
clock and will vary from chip-to-chip due to temperature
and process variation. See DC Parameter 33 for
details.
5.6.1
TIME-OUT SEQUENCE
If enabled, the PWRT time-out is invoked after the POR
pulse has cleared. The total time-out will vary based on
the status of the PWRT. Figure 5-3, Figure 5-4,
and
all
depict
time-out
sequences on power-up with the Power-up Timer
enabled.
Since the time-outs occur from the POR pulse, if
MCLR is kept low long enough, the PWRT will expire.
Bringing MCLR high will begin execution immediately
(Figure 5-5). This is useful for testing purposes or for
synchronizing more than one PIC18 device operating
in parallel.
FIGURE 5-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
TPWRT
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
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相關代理商/技術參數(shù) |
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| P89V51RB2FA | 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 16K FLASH PLCC44 |
| P89V51RB2FA,529 | 功能描述:8位微控制器 -MCU 80C51 16K FL / 512 R RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P89V51RB2FA529 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 40MHZ LCC-44 |
| P89V51RB2FN | 制造商:NXP Semiconductors 功能描述:IC MCU 8BIT 80C51 16K FLASH DIP40 制造商:NXP Semiconductors 功能描述:IC, MCU 8BIT 80C51 16K FLASH, DIP40 |
| P89V51RB2FN,112 | 功能描述:8位微控制器 -MCU 80C51 16K FL / 512 R RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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