參數(shù)資料
型號： P89LPC954FBD44,151
廠商： NXP Semiconductors
文件頁數(shù)： 30/69頁
文件大?。?/td> 0K
描述： IC 80C51 MCU FLASH 16K 44LQFP
標(biāo)準(zhǔn)包裝： 160
系列： LPC900
核心處理器： 8051
芯體尺寸： 8-位
速度： 18MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 40
程序存儲器容量： 16KB（16K x 8）
程序存儲器類型： 閃存
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LQFP
包裝： 托盤
配用： 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱： 568-7917
568-7917-ND
568-8269
935284303151
P89LPC954FBD44,151-ND
P89LPC954FBD44-S
P89LPC954FBD44-S-ND
P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
36 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
Double buffering can be disabled. If disabled (DBMOD_n, i.e., SnSTAT.7 = 0), the UART is
compatible with the conventional 80C51 UART. If enabled, the UART allows writing to
SnBUF while the previous data is being shifted out. Double buffering is only allowed in
Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled
(DBMOD_n = 0).
7.19.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the TI_n interrupt is generated
when the double buffer is ready to receive new data.
7.19.10 The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3)
If double buffering is disabled TB8_n can be written before or after SnBUF is written, as
long as TB8_n is updated some time before that bit is shifted out. TB8_n must not be
changed until the bit is shifted out, as indicated by the TI_n interrupt.
If double buffering is enabled, TB8_n must be updated before SnBUF is written, as TB8_n
will be double-buffered together with SnBUF data.
7.20 I2C-bus serial interface
I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected
to the bus, and it has the following features:
Bidirectional data transfer between masters and slaves
Multi master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I2C-bus may be used for test and diagnostic purposes.
A typical I2C-bus conguration is shown in Figure 9. The P89LPC952/954 device provides
a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.
Fig 9.
I2C-bus conguration
OTHER DEVICE
WITH I2C-BUS
INTERFACE
SDA
SCL
RPU
OTHER DEVICE
WITH I2C-BUS
INTERFACE
P1.3/SDA
P1.2/SCL
I2C MCU
I2C-bus
002aab410
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P89LPC954FBD44-S 功能描述:8位微控制器 -MCU 16K FL/1K RAM/512B EE/10B ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
P89LPC954FBD48 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC
P89LPC954FBD48,151 功能描述:8位微控制器 -MCU 8B MCU 2-CLOCK 80C51 8/16KB 3V 10B RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
P89LPC970 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB wide-voltage byte-erasable flash
P89LPC970FDH 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB wide-voltage byte-erasable flash
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