參數(shù)資料
型號: P89LPC954FBD44,151
廠商: NXP Semiconductors
文件頁數(shù): 16/69頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 16K 44LQFP
標(biāo)準(zhǔn)包裝: 160
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
配用: 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-7917
568-7917-ND
568-8269
935284303151
P89LPC954FBD44,151-ND
P89LPC954FBD44-S
P89LPC954FBD44-S-ND
P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
23 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.2 Enhanced CPU
The P89LPC952/954 uses an enhanced 80C51 CPU which runs at six times the speed of
standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most
instructions execute in one or two machine cycles.
7.3 Clocks
7.3.1 Clock denitions
The P89LPC952/954 device has several internal clocks as dened below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock
sources (see Figure 6) and can also be optionally divided to a slower frequency (see
Note: fosc is dened as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine
cycle, and most instructions are executed in one to two machine cycles (two or four CCLK
cycles).
RCCLK — The internal 7.373 MHz RC oscillator output. The clock doubler option, when
enabled, provides an output frequency of 14.746 MHz.
PCLK — Clock for the various peripheral devices and is CCLK
2.
7.3.2 CPU clock (OSCCLK)
The P89LPC952/954 provides several user-selectable oscillator options in generating the
CPU clock. This allows optimization for a range of needs from high precision to lowest
possible cost. These options are congured when the ash is programmed and include an
on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external
crystal, or an external clock source. The crystal oscillator can be optimized for low,
medium, or high frequency crystals covering a range from 20 kHz to 18 MHz.
7.3.3 Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this conguration.
7.3.4 Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this conguration.
7.3.5 High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this conguration. When using a clock frequency
above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit
is required to hold the device in reset at power-up until VDD has reached its
specied level. When system power is removed VDD will fall below the minimum
specied operating voltage. When using a clock frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the device
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