參數(shù)資料
型號： P89LPC954FBD44,151
廠商： NXP Semiconductors
文件頁數(shù)： 18/69頁
文件大小： 0K
描述： IC 80C51 MCU FLASH 16K 44LQFP
標準包裝： 160
系列： LPC900
核心處理器： 8051
芯體尺寸： 8-位
速度： 18MHz
連通性： I²C，SPI，UART/USART
外圍設備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數(shù)： 40
程序存儲器容量： 16KB（16K x 8）
程序存儲器類型： 閃存
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LQFP
包裝： 托盤
配用： 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱： 568-7917
568-7917-ND
568-8269
935284303151
P89LPC954FBD44,151-ND
P89LPC954FBD44-S
P89LPC954FBD44-S-ND
P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
25 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.7 CCLK wake-up delay
The P89LPC952/954 has an internal wake-up timer that delays the clock until it stabilizes
depending on the clock source used. If the clock source is any of the three crystal
selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus
60
sto100 s. If the clock source is either the internal RC oscillator, watchdog oscillator,
or external clock, the delay is 224 OSCCLK cycles plus 60
sto100 s.
7.8 CCLK modication: DIVM register
The OSCCLK frequency can be divided down up to 510 times by conguring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
7.9 Low power select
The P89LPC952/954 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK
is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power
consumption further. On any reset, CLKLP is ‘0’ allowing highest performance access.
This bit can then be set in software if CCLK is running at 8 MHz or slower.
Fig 6.
Block diagram of oscillator control
÷2
002aab409
RTC
ADC0
CPU
WDT
DIVM
CCLK
OSCCLK
HIGH FREQUENCY
MEDIUM FREQUENCY
LOW FREQUENCY
XTAL1
XTAL2
RC OSCILLATOR
WITH CLOCK DOUBLER
WATCHDOG
OSCILLATOR
(7.3728 MHz/14.7456 MHz
± 1 %)
PCLK
RCCLK
(400 kHz +30 %
20 %)
UARTS
I2C-BUS
PCLK
TIMER 0 AND
TIMER 1
SPI
RCCLK
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相關代理商/技術參數(shù)
參數(shù)描述
P89LPC954FBD44-S 功能描述:8位微控制器 -MCU 16K FL/1K RAM/512B EE/10B ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
P89LPC954FBD48 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC
P89LPC954FBD48,151 功能描述:8位微控制器 -MCU 8B MCU 2-CLOCK 80C51 8/16KB 3V 10B RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
P89LPC970 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB wide-voltage byte-erasable flash
P89LPC970FDH 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB wide-voltage byte-erasable flash
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