參數(shù)資料
型號(hào)： P89LPC932BDH
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller with two-clock core 8 KB 3 V low-power Flash with 512-byte data EEPROM
中文描述： 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PDSO28
封裝： 4.40 MM, PLASTIC, MO-153, SOT-361-1, TSSOP-28
文件頁(yè)數(shù)： 49/64頁(yè)
文件大?。?/td> 316K
代理商： P89LPC932BDH
9397 750 14871
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 10 May 2005
49 of 64
Philips Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
10. Dynamic characteristics
Table 10:
V
DD
= 2.4 V to 3.6 V unless otherwise specified.
T
amb
=
40
°
C to +85
°
C for industrial applications, unless otherwise specified.
[1] [2]
Symbol
Parameter
Dynamic characteristics (12 MHz)
Conditions
Variable clock
Min
7.189
280
f
osc
= 12 MHz
Min
7.189
280
Unit
Max
7.557
480
Max
7.557
480
f
OSC(RC)
f
OSC(WD)
internal RC oscillator frequency
internal watchdog oscillator
frequency
oscillator frequency
clock cycle time
low power select clock frequency
MHz
kHz
f
osc
T
cy(CLK)
f
CLKLP
Glitch filter
t
gr
0
12
-
8
-
-
-
-
-
-
MHz
ns
MHz
see
Figure 22
83
0
glitch rejection
P1.5/RST pin
any pin except
P1.5/RST
P1.5/RST pin
any pin except
P1.5/RST
-
-
50
15
-
-
50
15
ns
ns
t
sa
signal acceptance
125
50
-
-
125
50
-
-
ns
ns
External clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift register (UART mode 0)
t
XLXL
serial port clock cycle time
t
QVXH
output data set-up to clock rising
edge time
t
XHQX
output data hold after clock rising
edge time
t
XHDX
input data hold after clock rising
edge time
t
XHDV
input data valid to clock rising
edge time
SPI interface
f
SPI
SPI operating frequency
slave
master
t
SPICYC
SPI cycle time
slave
master
t
SPILEAD
SPI enable lead time
2.0 MHz (slave)
clock HIGH time
clock LOW time
clock rise time
clock fall time
see
Figure 22
see
Figure 22
see
Figure 22
see
Figure 22
33
33
-
-
T
cy(CLK)
t
CLCX
T
cy(CLK)
t
CHCX
8
8
33
33
-
-
-
-
8
8
ns
ns
ns
ns
see
Figure 21
see
Figure 21
16T
cy(CLK)
13T
cy(CLK)
-
-
1333
1083
-
-
ns
ns
see
Figure 21
-
T
cy(CLK)
+ 20
-
103
ns
see
Figure 21
-
0
-
0
ns
see
Figure 21
150
-
150
-
ns
0
-
CCLK
6
CCLK
4
0
-
2.0
3.0
MHz
MHz
see
Figure 23
,
24
,
25
,
26
6
CCLK
4
CCLK
-
-
500
333
-
-
ns
ns
see
Figure 25
,
26
250
-
250
-
ns
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