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參數(shù)資料
| 型號： | P89LPC932A1FA,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 38/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 8K 28-PLCC |
| 產(chǎn)品培訓模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標準包裝： | 37 |
| 系列： | LPC900 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 18MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，LED，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 26 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 768 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-PLCC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 706 (CN2011-ZH PDF) |
| 配用： | DB-TSSOP-LPC932-ND - BOARD FOR LPC932 TSSOP 622-1014-ND - BOARD FOR LPC9XX TSSOP 622-1008-ND - BOARD FOR LPC9103 10-HVSON 622-1006-ND - SOCKET ADAPTER BOARD 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART 568-3510-ND - DEMO BOARD SPI/I2C TO UART 622-1003-ND - KIT FOR LCD DEMO 622-1002-ND - USB IN-CIRCUIT PROG LPC9XX 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X 568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY |
| 其它名稱： | 568-4279-5 935276131112 P89LPC932A1FA |
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P89LPC932A1_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 12 March 2007
43 of 64
NXP Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
In addition, IAP operations can be accomplished through the use of four SFRs consisting
of a control/status register, a data register, and two address registers. Additional details
may be found in the P89LPC932A1
User manual.
7.28.8 In-system programming
ISP is performed without removing the microcontroller from the system. The ISP facility
consists of a series of internal hardware resources coupled with internal rmware to
facilitate remote programming of the P89LPC932A1 through the serial port. This rmware
is provided by NXP and embedded within each P89LPC932A1 device. The ISP facility has
made ISP in an embedded application possible with a minimum of additional expense in
components and circuit board area. The ISP function uses ve pins (VDD,VSS, TXD, RXD,
and RST). Only a small connector needs to be available to interface your application to an
external circuit in order to use this feature.
7.28.9 Power-on reset code execution
The P89LPC932A1 contains two special ash elements: the Boot Vector and the Boot
Status Bit. Following reset, the P89LPC932A1 examines the contents of the Boot Status
Bit. If the Boot Status Bit is set to zero, power-up execution starts at location 0000H, which
is the normal start address of the user’s application code. When the Boot Status Bit is set
to a value other than zero, the contents of the Boot Vector are used as the high byte of the
execution address and the low byte is set to 00H.
Table 6 shows the factory default Boot Vector settings for these devices. Note: These
settings are different than the original P89LPC932. Tools designed to support the
P89LPC932A1 should be used to program this device, such as Flash Magic version
1.98, or later. A factory-provided boot loader is preprogrammed into the address space
indicated and uses the indicated boot loader entry point to perform ISP functions. This
code can be erased by the user. Users who wish to use this loader should take
precautions to avoid erasing the 1 kB sector that contains this boot loader. Instead,
the page erase function can be used to erase the rst eight 64-byte pages located in
this sector. A custom boot loader can be written with the Boot Vector set to the custom
boot loader, if desired.
7.28.10 Hardware activation of the boot loader
The boot loader can also be executed by forcing the device into ISP mode during a
power-on sequence (see the P89LPC932A1
User manual for specic information). This
has the same effect as having a non-zero status byte. This allows an application to be built
that will normally execute user code but can be manually forced into ISP operation. If the
factory default setting for the Boot Vector (1FH) is changed, it will no longer point to the
factory preprogrammed ISP boot loader code. After programming the ash, the status
byte should be programmed to zero in order to allow execution of the user’s application
code beginning at address 0000H.
Table 6.
Default Boot Vector values and ISP entry points
Device
Default
Boot Vector
Default
boot loader
entry point
Default boot loader
code range
1 kB sector
range
P89LPC932A1
1FH
1F00H
1E00H to 1FFFH
1C00H to 1FFFH
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| P89LPC932A1FDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM |
| P89LPC932A1FDH,512 | 功能描述:8位微控制器 -MCU 80C51 8K FL 768B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P89LPC932A1FDH,529 | 功能描述:8位微控制器 -MCU 8K FL/768B RAM/512B EE/CCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P89LPC932A1FDH512 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 18MHZ TSSOP-28 |
| P89LPC932A1FHN | 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 8K FLASH HVQFN-28 |
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