參數(shù)資料
型號(hào): P89LPC932A1FA,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 24/64頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 28-PLCC
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 37
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-PLCC
包裝: 管件
產(chǎn)品目錄頁(yè)面: 706 (CN2011-ZH PDF)
配用: DB-TSSOP-LPC932-ND - BOARD FOR LPC932 TSSOP
622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1003-ND - KIT FOR LCD DEMO
622-1002-ND - USB IN-CIRCUIT PROG LPC9XX
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱: 568-4279-5
935276131112
P89LPC932A1FA
P89LPC932A1_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 12 March 2007
30 of 64
NXP Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
7.19.9 CCU interrupts
There are seven interrupt sources on the CCU which share a common interrupt vector.
7.20 UART
The P89LPC932A1 has an enhanced UART that is compatible with the conventional
80C51 UART except that Timer 2 overow cannot be used as a baud rate source. The
P89LPC932A1 does include an independent Baud Rate Generator. The baud rate can be
selected from the oscillator (divided by a constant), Timer 1 overow, or the independent
Baud Rate Generator. In addition to the baud rate generation, enhancements over the
standard 80C51 UART include Framing Error detection, automatic address recognition,
selectable double buffering and several interrupt options. The UART can be operated in
four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.
7.20.1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are
transmitted or received, LSB rst. The baud rate is xed at 1
16 of the CPU clock
frequency.
7.20.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),
8 data bits (LSB rst), and a stop bit (logic 1). When data is received, the stop bit is stored
in RB8 in Special Function Register SCON. The baud rate is variable and is determined
by the Timer 1 overow rate or the Baud Rate Generator (described in Section 7.20.5
Fig 12. Capture/compare unit interrupts
002aaa896
interrupt to
CPU
TOIE2 (TICR2.7)
TOIF2 (TIFR2.7)
TICIE2A (TICR2.0)
TICF2A (TIFR2.0)
TICIE2B (TICR2.1)
TICF2B (TIFR2.1)
TOCIE2A (TICR2.3)
TOCF2A (TIFR2.3)
TOCIE2B (TICR2.4)
TOCF2B (TIFR2.4)
TOCIE2C (TICR2.5)
TOCF2C (TIFR2.5)
TOCIE2D (TICR2.6)
TOCF2D (TIFR2.6)
EA (IEN0.7)
ECCU (IEN1.4)
PRIORITY
ENCODER
other
interrupt
sources
ENCINT.0
ENCINT.1
ENCINT.2
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