參數(shù)資料
型號(hào)： P89LPC924FDH
廠商： NXP Semiconductors N.V.
元件分類： 8位微控制器
英文描述： 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB-8 kB 3 V low-power Flash with 8-bit A-D converter
封裝： P89LPC924FDH<SOT360-1 (TSSOP20)|<<http://www.nxp.com/packages/SOT360-1.html<1<Always Pb-free,;P89LPC925FDH<SOT360-1 (TSSOP20)|<<http://www.nxp.com/packages/SOT360-1.html&
文件頁(yè)數(shù)： 9/49頁(yè)
文件大?。?/td> 233K
代理商： P89LPC924FDH
Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data
Rev. 03 — 15 December 2004
17 of 49
9397 750 14471
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.6 CPU Clock (CCLK) wake-up delay
The P89LPC924/925 has an internal wake-up timer that delays the clock until it
stabilizes depending to the clock source used. If the clock source is any of the three
crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK
cycles plus 60 to 100
s. If the clock source is either the internal RC oscillator,
watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plus
60 to 100
s.
8.7 CPU Clock (CCLK) modication: DIVM register
The OSCCLK frequency can be divided down up to 510 times by conguring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPU at a lower rate, reducing power consumption. By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
mode by executing its normal program at a lower rate. This can also allow bypassing
the oscillator start-up time in cases where Power-down mode would otherwise be
used. The value of DIVM may be changed by the program at any time without
interrupting code execution.
8.8 Low power select
The P89LPC924/925 is designed to run at 18 MHz (CCLK) maximum. However, if
CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the
power consumption further. On any reset, CLKLP is ‘0’ allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
相關(guān)PDF資料
PDF描述
P89LPC925FDH 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB-8 kB 3 V low-power Flash with 8-bit A-D converter
P89LPC9301FDH 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB-8 kB 3 V byte-erasable flash
P89LPC931A1FDH 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB-8 kB 3 V byte-erasable flash
P89LPC930FDH 8-bit microcontrollers with two-clock 80C51 core 4 kB-8 kB 3 V Flash with 256-byte data RAM
P89LPC931FDH 8-bit microcontrollers with two-clock 80C51 core 4 kB-8 kB 3 V Flash with 256-byte data RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
P89LPC924FDH,518 功能描述:8位微控制器 -MCU 4K FL/256B RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
P89LPC924FDH,529 功能描述:8位微控制器 -MCU ORDER P89LPC924FDH-T T/R RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
P89LPC924FDH518 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 18MHZ TSSOP-20
P89LPC924FDH-S 功能描述:8位微控制器 -MCU 80C51 4K FL 256B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
P89LPC924FDH-T 功能描述:8位微控制器 -MCU 4K FL/256B RAM/I2C/UART/ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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