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| 型號： | P89LPC924FDH |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB-8 kB 3 V low-power Flash with 8-bit A-D converter |
| 封裝： | P89LPC924FDH<SOT360-1 (TSSOP20)|<<http://www.nxp.com/packages/SOT360-1.html<1<Always Pb-free,;P89LPC925FDH<SOT360-1 (TSSOP20)|<<http://www.nxp.com/packages/SOT360-1.html& |
| 文件頁數(shù)： | 24/49頁 |
| 文件大?。?/td> | 233K |
| 代理商： | P89LPC924FDH |
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Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data
Rev. 03 — 15 December 2004
30 of 49
9397 750 14471
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.19.6
Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0
(PCON.6) is ‘1’, framing errors can be made available in SCON.7 respectively. If
SMOD0 is ‘0’, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6)
are set up when SMOD0 is ‘0’.
8.19.7
Break detect
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the
device and force the device into ISP mode.
8.19.8
Double buffering
The UART has a transmit double buffer that allows buffering of the next character to
be written to SBUF while the rst character is being transmitted. Double buffering
allows transmission of a string of characters with only one stop bit between any two
characters, as long as the next character is written between the start bit and the stop
bit of the previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = ‘0’), the UART
is compatible with the conventional 80C51 UART. If enabled, the UART allows writing
to SnBUF while the previous data is being shifted out. Double buffering is only
allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be
disabled (DBMOD = ‘0’).
8.19.9
Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated
when the double buffer is ready to receive new data.
8.19.10
The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as
long as TB8 is updated some time before that bit is shifted out. TB8 must not be
changed until the bit is shifted out, as indicated by the Tx interrupt.
If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8
will be double-buffered together with SBUF data.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P89LPC924FDH,518 | 功能描述:8位微控制器 -MCU 4K FL/256B RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89LPC924FDH,529 | 功能描述:8位微控制器 -MCU ORDER P89LPC924FDH-T T/R RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89LPC924FDH518 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 18MHZ TSSOP-20 |
| P89LPC924FDH-S | 功能描述:8位微控制器 -MCU 80C51 4K FL 256B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89LPC924FDH-T | 功能描述:8位微控制器 -MCU 4K FL/256B RAM/I2C/UART/ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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