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參數(shù)資料
| 型號： | P89LPC924 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converter |
| 中文描述： | 8 -加速雙位單片機80C51的時鐘4 KB的核心/ 8 KB的3伏的低功耗Flash 8位A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 43/49頁 |
| 文件大?。?/td> | 233K |
| 代理商： | P89LPC924 |
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Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data
Rev. 03 — 15 December 2004
43 of 49
9397 750 14471
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until V
DD
has reached its specified level. When system power is removed V
DD
will fall below the
minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout
detect circuit may be required to hold the device in reset when V
DD
falls below the minimum specified operating voltage.
[2]
Table 10:
V
DD
= 3.0 V to 3.6 V unless otherwise specified.
T
amb
=
40
°
C to +85
°
C for industrial, unless otherwise specified.
[1]
Symbol
Parameter
AC characteristics
Conditions
Variable clock
Min
7.189
f
osc
= 18 MHz
Min
7.189
Unit
Max
7.557
Max
7.557
f
RCOSC
internal RC oscillator frequency
(nominal f = 7.3728 MHz)
internal Watchdog oscillator
frequency (nominal f = 400 kHz)
oscillator frequency
clock cycle
CLKLP active frequency
Glitch filter
glitch rejection, P1.5/RST pin
signal acceptance, P1.5/RST pin
glitch rejection, any pin except
P1.5/RST
signal acceptance, any pin except
P1.5/RST
External clock
t
CHCX
HIGH time
t
CLCX
LOW time
t
CLCH
rise time
t
CHCL
fall time
Shift register (UART mode 0)
t
XLXL
serial port clock cycle time
t
QVXH
output data set-up to clock rising
edge
t
XHQX
output data hold after clock rising
edge
t
XHDX
input data hold after clock rising
edge
t
DVXH
input data valid to clock rising edge
trimmed to
±
1%
at T
amb
= 25
°
C
MHz
f
WDOSC
320
520
320
520
kHz
f
osc
t
CLCL
f
CLKP
[2]
0
55
0
18
-
8
-
-
-
-
-
-
MHz
ns
MHz
see
Figure 13
-
125
-
50
-
15
-
125
-
50
-
15
ns
ns
ns
50
-
50
-
ns
see
Figure 13
see
Figure 13
see
Figure 13
see
Figure 13
22
22
-
-
t
CLCL
t
CLCX
t
CLCL
t
CHCX
5
5
22
22
-
-
-
-
5
5
ns
ns
ns
ns
16 t
CLCL
13 t
CLCL
-
-
888
722
-
-
ns
ns
-
t
CLCL
+ 20
-
75
ns
-
0
-
0
ns
150
-
150
-
ns
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| P89LPC9241 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB 3 V byte-erasable flash with 8-bit ADC |
| P89LPC9241FDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB 3 V byte-erasable flash with 8-bit ADC |
| P89LPC9241FDH,112 | 功能描述:8位微控制器 -MCU MCU 8-Bit CISC 4KB Flash2.5V/3.3V 20Pin RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P89LPC924FDH | 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 4K FLASH TSSOP20 |
| P89LPC924FDH,518 | 功能描述:8位微控制器 -MCU 4K FL/256B RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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