參數(shù)資料
型號: P89LPC924
廠商: NXP Semiconductors N.V.
英文描述: 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converter
中文描述: 8 -加速雙位單片機80C51的時鐘4 KB的核心/ 8 KB的3伏的低功耗Flash 8位A / D轉換器
文件頁數(shù): 36/49頁
文件大小: 233K
代理商: P89LPC924
Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data
Rev. 03 — 15 December 2004
36 of 49
9397 750 14471
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.25 Flash program memory
8.25.1
General description
The P89LPC924/925 Flash memory provides in-circuit electrical erasure and
programming. The Flash can be read, erased, or written as bytes. The Sector and
Page Erase functions can erase any Flash sector (1 kB) or page (64 bytes). The Chip
Erase operation will erase the entire program memory. In-System Programming and
standard parallel programming are both available. On-chip erase and write timing
generation contribute to a user-friendly programming interface. The P89LPC924/925
Flash reliably stores memory contents even after 100,000 erase and program cycles.
The cell is designed to optimize the erase and programming mechanisms. The
P89LPC924/925 uses V
DD
as the supply voltage to perform the Program/Erase
algorithms.
8.25.2
Features
Parallel programming with industry-standard commercial programmers.
In-Circuit serial Programming (ICP) with industry-standard commercial
programmers.
IAP-Lite allows individual and multiple bytes of code memory to be used for data
storage and programmed under control of the end application.
Internal fixed boot ROM, containing low-level In-Application Programming (IAP)
routines that can be called from the end application (in addition to IAP-Lite).
Default serial loader providing In-System Programming (ISP) via the serial port,
located in upper end of user program memory.
Boot vector allows user-provided Flash loader code to reside anywhere in the
Flash memory space, providing flexibility to the user.
Programming and erase over the full operating voltage range.
Read/Programming/Erase using ISP/IAP/IAP-Lite.
Any flash program operation in 2 ms.
Any flash erase operation in 4 ms.
Programmable security for the code in the Flash for each sector.
>100,000 typical erase/program cycles for each byte.
10 year minimum data retention.
8.25.3
ISP and IAP capabilities of the P89LPC924/925
Flash organization:
The P89LPC924/925 program memory consists of four/eight
1 kB sectors. Each sector can be further divided into 64-byte pages. In addition to
sector erase, page erase, and byte erase, a 64-byte page register is included which
allows from 1 to 64 bytes of a given page to be programmed at the same time,
substantially reducing overall programming time. An In-Application Programming
(IAP) interface is provided to allow the end user’s application to erase and reprogram
the user code memory. In addition, erasing and reprogramming of
user-programmable bytes including UCFG1, the Boot Status Byte and the Boot
Vector are supported. As shipped from the factory, the upper 512 bytes of user code
space contains a serial In-System Programming (ISP) routine allowing for the device
to be programmed in circuit through the serial port.
相關PDF資料
PDF描述
P89LPC925 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converter
P89LPC930 8-bit microcontrollers with two-clock 80C51 core 4 kB/8 kB 3 V Flash with 256-byte data RAM
P89LPC933 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable Flash with 8-bit A/D converters
P89LPC934 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable Flash with 8-bit A/D converters
P89LPC935 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable Flash with 8-bit A/D converters
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