參數(shù)資料
型號: P89LPC9241FDH
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 2 kB-4 kB-8 kB 3 V byte-erasable flash with 8-bit ADC
中文描述: MICROCONTROLLER, PDSO20
封裝: 4.40 MM, PLASTIC, MO-153, SOT360-1, TSSOP-20
文件頁數(shù): 38/75頁
文件大?。?/td> 1612K
代理商: P89LPC9241FDH
P89LPC92X1
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 1 December 2010
43 of 75
NXP Semiconductors
P89LPC9201/9211/922A1/9241/
8-bit microcontroller with 8-bit ADC
7.27 Additional features
7.27.1 Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog reset had occurred. Care should be taken when writing
to AUXR1 to avoid accidental software resets.
7.27.2 Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects one of
the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS
bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1
register, without the possibility of inadvertently altering other bits in the register.
7.28 Flash program memory
7.28.1 General description
The P89LPC9201/9211/922A1/9241/9251 flash memory provides in-circuit electrical
erasure and programming. The flash can be erased, read, and written as bytes. The
Sector and Page Erase functions can erase any flash sector (1 kB) or page (64 bytes).
The Chip Erase operation will erase the entire program memory. ICP using standard
commercial programmers is available. In addition, IAP and byte-erase allows code
memory to be used for non-volatile data storage. On-chip erase and write timing
generation contribute to a user-friendly programming interface. The
P89LPC9201/9211/922A1/9241/9251 flash reliably stores memory contents even after
100,000 erase and program cycles. The cell is designed to optimize the erase and
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed
sequence.
Fig 14. Watchdog timer in Watchdog mode (WDTE = 1)
PRE2
PRE1
PRE0
-
WDRUN
WDTOF
WDCLK
WDCON (A7H)
SHADOW REGISTER
PRESCALER
002aae015
8-BIT DOWN
COUNTER
WDL (C1H)
watchdog
oscillator
crystal
oscillator
PCLK
XTALWD
÷32
0
1
0
1
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
reset(1)
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