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參數(shù)資料
| 型號(hào)： | P89LPC9241FDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit microcontroller with accelerated two-clock 80C51 core 2 kB-4 kB-8 kB 3 V byte-erasable flash with 8-bit ADC |
| 中文描述： | MICROCONTROLLER, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT360-1, TSSOP-20 |
| 文件頁數(shù)： | 21/75頁 |
| 文件大小： | 1612K |
| 代理商： | P89LPC9241FDH |
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P89LPC92X1
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 1 December 2010
28 of 75
NXP Semiconductors
P89LPC9201/9211/922A1/9241/
8-bit microcontroller with 8-bit ADC
7.10 CCLK wake-up delay
The P89LPC9201/9211/922A1/9241/9251 has an internal wake-up timer that delays the
clock until it stabilizes depending on the clock source used. If the clock source is any of
the three crystal selections (low, medium and high frequencies) the delay is
1024 OSCCLK cycles plus 60
μsto100 μs. If the clock source is the internal RC
oscillator, the delay is 200
μs to 300 μs. If the clock source is watchdog oscillator or
external clock, the delay is 32 OSCCLK cycles.
7.11 CCLK modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
7.12 Low power select
The P89LPC9201/9211/922A1/9241/9251 is designed to run at 18 MHz (CCLK)
maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be
set to logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0
allowing highest performance access. This bit can then be set in software if CCLK is
running at 8 MHz or slower.
Fig 8.
Block diagram of oscillator control
÷2
002aae428
RTC
ADC
(P89LPC9241/9251)
CPU
WDT
DIVM
CCLK
UART
OSCCLK
I2C-BUS
PCLK
TIMER 0 AND
TIMER 1
HIGH FREQUENCY
MEDIUM FREQUENCY
LOW FREQUENCY
XTAL1
XTAL2
RC OSCILLATOR
WITH CLOCK DOUBLER
WATCHDOG
OSCILLATOR
(7.3728 MHz/14.7456 MHz
± 1 %)
PCLK
RCCLK
(400 kHz
± 5 %)
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| P89LPC9241FDH,112 | 功能描述:8位微控制器 -MCU MCU 8-Bit CISC 4KB Flash2.5V/3.3V 20Pin RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89LPC924FDH | 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 4K FLASH TSSOP20 |
| P89LPC924FDH,518 | 功能描述:8位微控制器 -MCU 4K FL/256B RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89LPC924FDH,529 | 功能描述:8位微控制器 -MCU ORDER P89LPC924FDH-T T/R RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89LPC924FDH518 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 18MHZ TSSOP-20 |
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