參數(shù)資料
型號(hào): P89LPC915
廠商: NXP Semiconductors N.V.
英文描述: 8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V Flash with 8-bit A/D converter
中文描述: 8 - 8加速雙位單片機(jī)80C51的時(shí)鐘核心2 Kb的3伏閃存位A / D轉(zhuǎn)換器
文件頁(yè)數(shù): 53/72頁(yè)
文件大小: 344K
代理商: P89LPC915
Philips Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data
Rev. 04 — 17 December 2004
53 of 72
9397 750 14397
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
can only be reset by a power-on reset. When the Watchdog feature is disabled, it can
be used as an interval timer and may generate an interrupt.
Figure 21
shows the
Watchdog timer in Watchdog mode. Feeding the Watchdog requires a two-byte
sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down,
the Watchdog is disabled. The Watchdog timer has a time-out period that ranges
from a few
μ
s to a few seconds. Please refer to the P89LPC915/916/917 User’s
Manualfor more details.
9.27 Additional features
9.27.1
Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor
completely, as if an external reset or Watchdog reset had occurred. Care should be
taken when writing to AUXR1 to avoid accidental software resets.
9.27.2
Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects
one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that
the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing
the AUXR1 register, without the possibility of inadvertently altering other bits in the
register.
9.28 Flash program memory
9.28.1
General description
The P89LPC915/916/917 Flash memory provides in-circuit electrical erasure and
programming. The Flash can be erased, read, and written as bytes. The Sector and
Page Erase functions can erase any Flash sector (256 bytes) or page (16 bytes). The
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a
feed sequence.
Fig 21. Watchdog timer in Watchdog mode (WDTE = 1).
PRE2
PRE1
PRE0
WDRUN
WDTOF
WDCLK
WDCON (A7H)
CONTROL REGISTER
PRESCALER
002aaa423
SHADOW
REGISTER
FOR WDCON
8-BIT DOWN
COUNTER
WDL (C1H)
Watchdog
oscillator
PCLK
÷
32
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
RESET
see note (1)
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