參數(shù)資料
型號: P89LPC912
廠商: NXP Semiconductors N.V.
英文描述: 8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM
中文描述: 8位微控制器兩個小時80C51的核心具有1KB 3伏閃光的128字節(jié)RAM
文件頁數(shù): 52/63頁
文件大小: 314K
代理商: P89LPC912
Philips Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 03 — 17 December 2004
52 of 63
9397 750 14468
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
SPI interface
f
SPI
Operating frequency
2.0 MHz (Slave)
3.0 MHz (Master)
Cycle time
0
-
CCLK
6
CCLK
4
0
-
2.0
-
MHz
MHz
t
SPICYC
see
Figure 24
,
25
,
26
,
27
2.0 MHz (Slave)
3.0 MHz (Master)
Enable lead time (Slave)
6
CCLK
4
CCLK
-
-
500
-
-
-
ns
ns
t
SPILEAD
see
Figure 26
,
27
2.0 MHz
Enable lag time (Slave)
250
-
250
-
ns
t
SPILAG
see
Figure 26
,
27
2.0 MHz
SPICLK high time
250
-
250
-
ns
t
SPICLKH
see
Figure 24
,
25
,
26
,
27
Master
Slave
SPICLK low time
2
CCLK
3
CCLK
-
-
340
190
-
-
ns
ns
t
SPICLKL
see
Figure 24
,
25
,
26
,
27
Master
Slave
Data set-up time (Master or Slave) see
Figure 24
,
2
CCLK
3
CCLK
100
-
-
-
340
190
100
-
-
-
ns
ns
ns
t
SPIDSU
25
,
26
,
27
see
Figure 24
,
25
,
26
,
27
see
Figure 26
,
27
see
Figure 26
,
27
t
SPIDH
Data hold time (Master or Slave)
100
-
100
-
ns
t
SPIA
Access time (Slave)
0
120
0
120
ns
t
SPIDIS
Disable time (Slave)
2.0 MHz
Enable to output data valid
0
240
-
240
ns
t
SPIDV
see
Figure 24
,
25
,
26
,
27
2.0 MHz
3.0 MHz
Output data hold time
0
0
0
240
167
-
-
-
0
240
167
-
ns
ns
ns
t
SPIOH
see
Figure 24
,
25
,
26
,
27
Table 14:
V
DD
= 2.4 V to 3.6 V unless otherwise specified.
T
amb
=
40
°
C to +85
°
C for industrial, unless otherwise specified.
[1]
Symbol
Parameter
AC characteristics
…continued
Conditions
Variable clock
Min
f
osc
= 12 MHz
Min
Unit
Max
Max
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