參數(shù)資料
型號： P89LPC912
廠商： NXP Semiconductors N.V.
英文描述： 8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM
中文描述： 8位微控制器兩個小時80C51的核心具有1KB 3伏閃光的128字節(jié)RAM
文件頁數(shù)： 29/63頁
文件大?。?/td> 314K
代理商： P89LPC912
Philips Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 03 — 17 December 2004
29 of 63
9397 750 14468
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.6 CPU Clock (CCLK) wake-up delay
The P89LPC912/913/914 has an internal wake-up timer that delays the clock until it
stabilizes, depending to the clock source used. If the clock source is any of the three
crystal selections (P89LPC912, P89LPC913) the delay is 992 OSCCLK cycles plus
60 to 100
μ
s. If the clock source is either the internal RC oscillator, Watchdog
oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60 to 100
μ
s.
9.7 CPU Clock (CCLK) modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPU at a lower rate, reducing power consumption. By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
mode by executing its normal program at a lower rate. This can also allow bypassing
the oscillator start-up time in cases where Power-down mode would otherwise be
used. The value of DIVM may be changed by the program at any time without
interrupting code execution.
9.8 Low power select
The P89LPC912 and P89LPC913 are designed to run at 18 MHz (CCLK) maximum.
However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’
to lower the power consumption further. On any reset, CLKLP is ‘0’ allowing highest
performance access. This bit can then be set in software if CCLK is running at 8 MHz
or slower.
9.9 Memory organization
The various P89LPC912/913/914 memory spaces are as follows:
DATA
128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area.
Fig 12. Block diagram of oscillator control (P89LPC914).
002aaa483
RTC
CPU
WDT
SPI
DIVM
CCLK
OSCCLK
PCLK
Peripheral clock
TIMER 0 and
TIMER 1
RC
OSCILLATOR
WATCHDOG
OSCILLATOR
(7.3728 MHz)
(400 kHz)
Oscillator
clock
CPU
clock
UART
BAUD RATE
GENERATOR
CCLK
2
相關PDF資料
PDF描述
P89LPC913 8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM
P89LPC914 8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM
P89LPC914FDH 8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM
P89LPC924 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converter
P89LPC925 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converter
相關代理商/技術參數(shù)
參數(shù)描述
P89LPC912FDH 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 1K FLASH TSSOP14 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 1K FLASH, TSSOP14
P89LPC912FDH,129 功能描述:8位微控制器 -MCU 80C51 1K FL 128B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
P89LPC912FDH129 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 18MHZ TSSOP-14
P89LPC912HDH 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontrollers with two-clock 80C51 core, 1 kB 3 V flash with 128-byte RAM
P89LPC913 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM
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