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參數(shù)資料
| 型號： | P89LPC9103 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter |
| 中文描述： | 8位微控制器兩個小時加速80C51的核心具有1KB 3伏字節(jié)可擦除閃存的8位A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 26/58頁 |
| 文件大?。?/td> | 257K |
| 代理商： | P89LPC9103 |
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9397 750 14655
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 April 2005
26 of 58
Philips Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
8.2 Enhanced CPU
The P89LPC9102/9103/9107 uses an enhanced 80C51 CPU which runs at six times the
speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and
most instructions execute in one or two machine cycles.
8.3 Clocks
8.3.1
Clock definitions
The P89LPC9102/9103/9107 device has internal clocks as defined below:
OSCCLK —
Input to the DIVM clock divider. OSCCLK is selected from one of the clock
sources (see
Figure 10 “Block diagram of P89LPC9102 oscillator control.”
) and can also
be optionally divided to a slower frequency (see
Section 8.8 “CCLK modification: DIVM
register”
).
Note:
f
osc
is defined as the OSCCLK frequency.
CCLK —
CPU clock; output of the clock divider. There are two CCLK cycles per machine
cycle, and most instructions are executed in one to two machine cycles (two or four CCLK
cycles).
RCCLK —
The internal 7.373 MHz RC oscillator output. The clock doubler option, when
enabled, provides an output frequency of 14.746 MHz.
PCLK —
Clock for the various peripheral devices and is
CCLK
2
.
8.3.2
CPU clock (OSCCLK)
The P89LPC9102/9103/9107 provides user-selectable oscillator options in generating the
CPU clock. This allows optimization for a range of needs from high precision to lowest
possible cost. These options are configured when the flash memory is programmed and
include an on-chip watchdog oscillator, an on-chip RC oscillator, and an external clock
input.
8.4 On-chip RC oscillator option
The P89LPC9102/9103/9107 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed value to adjust the oscillator frequency to 7.373 MHz
±
1 % at room
temperature. End-user applications can write to the Trim register to adjust the on-chip RC
oscillator to other frequencies. When the clock doubler option is enabled (UCFG1.3 = 1)
the output frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit
(AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0
allowing highest performance access. This bit can then be set in software if CCLK is
running at 8 MHz or slower.
The RCCLK bit (TRIM.7) can be used to switch between the clock source selected by
UCFG1 and the internal RC oscillator. This allows a low frequency source such as the
WDT or low speed external source to clock the device in order to save power and then
switch to the higher speed internal RC oscillator to perform processing.
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P89LPC9103FTK | 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 1K FLASH HVSON-10 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 1K FLASH, HVSON-10 |
| P89LPC9103FTK,115 | 功能描述:8位微控制器 -MCU 80C51 1K FL 128B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P89LPC9107 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable flash with 8-bit A/D converter |
| P89LPC9107FDH | 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 1K FLASH TSSOP14 |
| P89LPC9107FDH,129 | 功能描述:8位微控制器 -MCU 80C51 1K FL 128B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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